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rev.3.02 nov 05, 2004 page 1 of 108 3803 group (spec.h) single-chip 8-bit cmos microcomputer rej03b0017-0302z rev.3.02 nov 05, 2004 preliminary notice: this is not a final specification. some parametric limits are subject to change. m38034m4h-xxxsp m38034m4h-xxxfp m38034m4h-xxxhp m38034m4h-xxxkp m38037m6h-xxxsp m38037m6h-xxxfp m38037m6h-xxxhp m38037m6h-xxxkp m38037m8h-xxxsp m38037m8h-xxxfp m38037m8h-xxxhp m38037m8h-xxxkp m38037m8h-xxxwg M38039mch-xxxsp M38039mch-xxxfp M38039mch-xxxhp M38039mch-xxxkp M38039mfh-xxxsp M38039mfh-xxxfp M38039mfh-xxxhp M38039mfh-xxxkp M38039mfh-xxxwg 3803 group (spec. h) mask rom version description the 3803 group (spec. h) is the 8-bit microcomputer based on the 740 family core technology. the 3803 group (spec. h) is designed for household products, of- fice automation equipment, and controlling systems that require analog signal processing, including the a-d converter and d-a converters. features basic machine-language instructions ...................................... 71 minimum instruction execution time ................................ 0.24 s (at 16.8 mhz oscillation frequency) memory size rom ............................................................... 16 k to 60 k bytes ram ................................................................. 640 to 2048 bytes programmable input/output ports ............................................ 56 software pull-up resistors ................................................. built-in interrupts 21 sources, 16 vectors ................................................................. (external 8, internal 12, software 1) timers ........................................................................... 16-bit ? 1 8-bit ? 4 (with 8-bit prescaler) watchdog timer ............................................................ 16-bit ? 1 serial i/o ...................... 8-bit ? 2 (uart or clock-synchronized) 8-bit ? 1 (clock-synchronized) pwm ............................................ 8-bit ? 1 (with 8-bit prescaler) a-d converter ............................................. 10-bit ? 16 channels (8-bit reading enabled) d-a converter ................................................. 8-bit ? 2 channels led direct drive port .................................................................. 8 clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode at 16.8 mhz oscillation frequency ............................ 4.5 to 5.5 v at 12.5 mhz oscillation frequency ............................ 4.0 to 5.5 v at 8.4 mhz oscillation frequency .............................. 2.7 to 5.5 v at 4.2 mhz oscillation frequency .............................. 2.2 to 5.5 v at 2.1 mhz oscillation frequency .............................. 2.0 to 5.5 v in middle-speed mode at 16.8 mhz oscillation frequency ............................ 4.5 to 5.5 v at 12.5 mhz oscillation frequency ............................ 2.7 to 5.5 v at 8.4 mhz oscillation frequency .............................. 2.2 to 5.5 v at 6.3 mhz oscillation frequency .............................. 1.8 to 5.5 v in low-speed mode at 32 khz oscillation frequency ................................. 1.8 to 5.5 v power dissipation in high-speed mode ................................................ 40 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ................................................... 45 w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range .................................... ?0 to 85? packages sp .................................................. 64p4b (64-pin 750 mil sdip) fp ....................................... 64p6n-a (64-pin 14 ? 14 mm qfp) hp ..................................... 64p6q-a (64-pin 10 ? 10 mm lqfp) kp ..................................... 64p6u-a (64-pin 14 ? 14 mm lqfp) wg ............................................ 64f0g (64-pin 6 ? 6 mm flga) currently support products are listed below. ram size (bytes) remarks package table 1 support products (mask rom version) product name 32768 (32638) rom size (bytes) rom size for user in ( ) 1024 64p4b 64p6n-a 64p6q-a 64p6u-a 64p4b 64p6n-a 64p6q-a 64p6u-a 64p4b 64p6n-a 64p6q-a 64p6u-a 64f0g 64p4b 64p6n-a 64p6q-a 64p6u-a 64p4b 64p6n-a 64p6q-a 64p6u-a 64f0g 16384 (16254) 640 24576 (24446) 1024 note: electrical characteristics differ by the 3803 group standard versions and the 3803 group (spec. h). since the 3803 group stan dard versions are not indicated to this data sheet, refer to ?803/3804 group data sheet? 61440 (61310) 2048 49152 (49022) 2048
rev.3.02 nov 05, 2004 page 2 of 108 3803 group (spec. h) flash memory version preliminary notice: this is not a final specification. some parametric limits are subject to change. description the 3803 group (spec. h) flash memory version is the 8-bit micro- computer based on the 740 family core technology. the 3803 group (spec. h) is designed for household products, of- fice automation equipment, and controlling systems that require analog signal processing, including the a-d converter and d-a converters. features basic machine-language instructions ...................................... 71 minimum instruction execution time ................................ 0.24 s (at 16.8 mhz oscillation frequency) memory size flash memory .............................................................. 60 k bytes ram ............................................................................ 2048 bytes programmable input/output ports ............................................ 56 software pull-up resistors ................................................. built-in interrupts 21 sources, 16 vectors ................................................................. (external 8, internal 12, software 1) timers ........................................................................... 16-bit ? 1 8-bit ? 4 (with 8-bit prescaler) watchdog timer ............................................................ 16-bit ? 1 serial i/o ...................... 8-bit ? 2 (uart or clock-synchronized) 8-bit ? 1 (clock-synchronized) pwm ............................................ 8-bit ? 1 (with 8-bit prescaler) a-d converter ............................................. 10-bit ? 16 channels (8-bit reading enabled) d-a converter ................................................. 8-bit ? 2 channels led direct drive port .................................................................. 8 clock generating circuit ..................................... b uilt-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode at 16.8 mhz oscillation frequency ............................ 4.5 to 5.5 v at 12.5 mhz oscillation frequency ............................ 4.0 to 5.5 v at 8.4 mhz oscillation frequency) ............................. 2.7 to 5.5 v in middle-speed mode at 16.8 mhz oscillation frequency ............................ 4.5 to 5.5 v at 12.5 mhz oscillation frequency ............................ 2.7 to 5.5 v in low-speed mode at 32 khz oscillation frequency ................................. 2.7 to 5.5 v power dissipation in high-speed mode ............................................. 27.5 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................... 1200 w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range .................................... 20 to 85 c packages sp .................................................. 64p4b (64-pin 750 mil sdip) fp ....................................... 64p6n-a (64-pin 14 ? 14 mm qfp) hp ..................................... 64p6q-a (64-pin 10 ? 10 mm lqfp) kp ..................................... 64p6u-a (64-pin 14 ? 14 mm lqfp) wg ............................................ 64f0g (64-pin 6 ? 6 mm flga) power source voltage ...................................... vcc = 2.7 to 5.5 v program/erase voltage .................................... vcc = 2.7 to 5.5 v programming method ...................... programming in unit of byte erasing method ...................................................... block erasing program/erase control by software command number of times for programming/erasing ............................ 100 notes the flash memory version cannot be used for application embed- ded in the mcu card. currently support products are listed below. ram size (bytes) remarks package table 2 support products (flash memory version) product name flash memory size (bytes) M38039ffhsp M38039ffhfp M38039ffhhp M38039ffhkp M38039ffhwg M38039ffsp M38039fffp M38039ffhp 64p4b 64p6n-a 64p6q-a 64p6u-a 64f0g 64p4b 64p6n-a 64p6q-a vcc = 2.7 to 5.5 v under development 61440 vcc = 4.0 to 5.5 v 2048 note: since description, features, and electrical charactristics etc. of M38039ffsp, M38039fffp, M38039ffhp are not indicated, refer to 3803/3804 group data sheet . 3803 group (spec. h) flash memory version
rev.3.02 nov 05, 2004 page 3 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) fig. 1 3803 group (spec. h) pin configuration package type : 64p6n-a/64p6q-a/64p6u-a 49 5 0 51 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 64 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 p 0 0 / a n 8 p 0 1 / a n 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p 0 4 / a n 1 2 p 0 5 / a n 1 3 p 0 6 / a n 1 4 p 0 7 / a n 1 5 p 1 0 / i n t 4 1 p 1 1 / i n t 0 1 p 1 2 p 1 3 p 1 6 p 1 4 p 1 5 p 1 7 p 2 7 ( l e d 7 ) p 2 0 ( l e d 0 ) p 2 1 ( l e d 1 ) p 2 2 ( l e d 2 ) p 2 3 ( l e d 3 ) p 2 4 ( l e d 4 ) p 2 5 ( l e d 5 ) p 2 6 ( l e d 6 ) v s s x o u t x i n p4 2 /int 1 r e s e t c n v s s p 4 0 / i n t 4 0 / x c o u t p 4 1 / i n t 0 0 / x c i n p 3 5 / t x d 3 p3 4 /r x d 3 p 3 1 / d a 2 p 3 0 / d a 1 v c c v r e f a v s s p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 3 7 / s r d y 3 p 3 6 / s c l k 3 p 3 3 p 3 2 p 6 1 / a n 1 p 6 0 / a n 0 p 5 7 / i n t 3 p 5 6 / p w m p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 4 6 / s c l k 1 p 4 5 / t x d 1 p 4 4 / r x d 1 p 4 3 / i n t 2 p 6 2 / a n 2 p 4 7 / s r d y 1 / c n t r 2 p 5 3 / s r d y 2 m 3 8 0 3 4 m 4 h - x x x f p / h p / k p m 3 8 0 3 7 m 6 h - x x x f p / h p / k p m 3 8 0 3 7 m 8 h - x x x f p / h p / k p m 3 8 0 3 9 m c h - x x x f p / h p / k p m 3 8 0 3 9 m f h - x x x f p / h p / k p m 3 8 0 3 9 f f h f p * / h p * / k p * 3 2 3 0 2 9 2 8 2 5 2 3 2 0 1 9 1 8 1 7 2 7 2 2 2 1 3 1 2 6 2 4 1 2 3 4 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 5 * u n d e r d e v e l o p m e n t ram size (bytes) remarks package table 3 list of package (spec. h) product name rom size (bytes) rom size for user in ( ) m38034m4h-xxxfp m38037m6h-xxxfp m38037m8h-xxxfp M38039mch-xxxfp M38039mfh-xxxfp M38039ffhfp* M38039fffp m38034m4h-xxxhp m38037m6h-xxxhp m38037m8h-xxxhp M38039mch-xxxhp M38039mfh-xxxhp M38039ffhhp* M38039ffhp m38034m4h-xxxkp m38037m6h-xxxkp m38037m8h-xxxkp M38039mch-xxxkp M38039mfh-xxxkp M38039ffhkp* mask rom version flash memory version flash memory version (vcc = 4.0 5.5 v) mask rom version flash memory version flash memory version (vcc = 4.0 5.5 v) mask rom version flash memory version 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) 61440 61440 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) 61440 61440 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) 61440 640 1024 1024 2048 2048 2048 2048 640 1024 1024 2048 2048 2048 2048 640 1024 1024 2048 2048 2048 64p6n-a * under development 64p6q-a 64p6u-a note: since description, features, and electrical charactristics etc. of M38039fffp and M38039ffhp are not indicated, refer to 3803/ 3804 group data sheet .
rev.3.02 nov 05, 2004 page 4 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) fig. 2 3803 group (spec. h) pin configuration package type : 64p4b v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 p3 3 p3 6 / s clk3 p3 7 / s rdy3 p4 7 /s rdy1 / cntr 2 m38034m4h-xxxsp m38037m6h-xxxsp m38037m8h-xxxsp M38039mch-xxxsp M38039mfh-xxxsp M38039ffhsp* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 64 * under develo p ment ram size (bytes) remarks package table 4 list of package (spec. h) product name rom size (bytes) rom size for user in ( ) m38034m4h-xxxsp m38037m6h-xxxsp m38037m8h-xxxsp M38039mch-xxxsp M38039mfh-xxxsp M38039ffhsp* M38039ffsp mask rom version flash memory version flash memory version (vcc = 4.0 5.5 v) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) 61440 61440 640 1024 1024 2048 2048 2048 2048 64p4b * under development note: since description, features, and electrical charactristics etc. of M38039ffsp are not indicated, refer to 3803/3804 group data sheet .
rev.3.02 nov 05, 2004 page 5 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) fig. 3 3803 group (spec. h) pin configuration package type : 64f0g (top) ram size (bytes) remarks package table 5 list of package (spec. h) product name rom size (bytes) rom size for user in ( ) m38037m8h-xxxwg M38039mfh-xxxwg M38039ffhwg* mask rom version flash memory version 32768 (32638) 61440 (61310) 61440 1024 2048 2048 64f0g * under development 3 2 1 8 7 6 5 4 abcdefgh 3 2 1 8 7 6 5 4 abcdefgh p6 1 /an 1 2 p6 5 /an 5 62 p6 7 /an 7 60 p6 2 /an 2 1 p3 0 /da 1 56 p3 3 53 p3 5 /t x d 3 51 p3 6 /s clk3 50 p6 0 /an 0 3 p6 4 /an 4 63 p6 6 /an 6 61 p6 3 /an 3 64 p3 1 /da 2 55 p3 4 /r x d 3 52 p0 1 /an 9 47 p0 2 /an 10 46 p5 5 /cntr 1 6 p5 6 /pwm 5 p5 7 /int 3 4 v ref 58 p3 2 54 p0 0 /an 8 48 p0 3 /an 11 45 p0 4 /an 12 44 p5 2 /s clk2 9 p5 3 /s rdy2 8 p5 4 /cntr 0 7 av ss 59 p3 7 /s rdy3 49 p0 5 /an 13 43 p0 6 /an 14 42 p0 7 /an 15 41 p5 0 /s in2 11 p5 1 /s out2 10 p4 7 /s rdy1 /cntr 2 12 v cc 57 p1 7 33 p1 2 38 p1 1 /int 01 39 p1 0 /int 41 40 p4 4 /r x d 1 15 p4 6 /s clk1 13 p4 5 /t x d 1 14 v ss 24 p1 4 36 p1 3 37 p2 5 (led 5 ) 27 p2 0 (led 0 ) 32 p4 3 /int 2 16 p4 2 /int 1 17 p4 0 /int 40 /x cout 21 x in 22 p1 5 35 p2 6 (led 6 ) 26 p2 3 (led 3 ) 29 p2 1 (led 1 ) 31 cnv ss 18 reset 19 p4 1 /int 00 /x cin 20 x out 23 p1 6 34 p2 7 (led 7 ) 25 p2 4 (led 4 ) 28 p2 2 (led 2 ) 30 * under development package (top view) m38037m8h -xxxwg M38039mfh -xxxwg M38039 ffhwg notes: the numbers in circles corresponds with the number on the packages fp/hp/kp. *
rev.3.02 nov 05, 2004 page 6 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. functional block diagram (package: 64p4b) fig. 4 functional block diagram functional block i n t 4 0 i n t 0 0 i n t 2 x i n o u t x r a m r o m c p u a x y s p c h p c l p s s s v 3 2 r e s e t 2 7 c c v 1 2 6 c n v s s c n t r 0 p 0 ( 8 ) 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 p 1 ( 8 ) 4 1 4 3 4 5 4 7 4 2 4 4 4 6 4 8 p 2 ( 8 ) 3 3 3 5 3 7 3 9 3 4 3 6 3 8 4 0 p 3 ( 8 ) 5 7 5 9 6 1 6 3 5 8 6 0 6 2 6 4 p 4 ( 8 ) 2 0 2 2 2 4 2 8 2 1 2 3 2 5 2 9 4 6 8 1 0 5 7 9 1 1 2 3 p 6 ( 8 ) i / o p o r t p 4 i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 ( l e d d r i v e ) i / o p o r t p 3 i / o p o r t p 6 c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t p r e s c a l e r 1 2 ( 8 ) t i m e r 1 ( 8 ) d a t a b u s c n t r 1 t i m e r z ( 1 6 ) a - d c o n v e r t e r ( 1 0 ) v r e f a v s s i n t 3 1 2 1 4 1 6 1 8 1 3 1 5 1 7 1 9 i / o p o r t p 5 p w m ( 8 ) p 5 ( 8 ) s i / o 2 ( 8 ) s i / o 1 ( 8 ) d - a c o n v e r t e r 1 ( 8 ) x c i n c o u t x 3 0 3 1 2 8 2 9 c n t r 2 s i / o 3 ( 8 ) i n t 0 1 i n t 4 1 i n t 1 c l o c k o u t p u t s u b - c l o c k i n p u t s u b - c l o c k o u t p u t r e s e t i n p u t t i m e r 2 ( 8 ) t i m e r x ( 8 ) t i m e r y ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) d - a c o n v e r t e r 2 ( 8 )
rev.3.02 nov 05, 2004 page 7 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pin description functions name pin apply voltage of 1.8 v 5.5 v to vcc, and 0 v to vss. in the flash memory version, apply volt- age of 2.7 v 5.5 v to vcc. this pin controls the operation mode of the chip. normally connected to v ss . reference voltage input pin for a-d and d-a converters. analog power source input pin for a-d and d-a converters. connect to v ss . reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. pull-up control is enabled in a bit unit. p2 0 p2 7 are enabled to output large current for led drive. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. p3 0 , p3 1 , p3 4 p3 7 are cmos 3-state output structure. p3 2 , p3 3 are n-channel open-drain output structure. pull-up control of p3 0 , p3 1 , p3 4 p3 7 is enabled in a bit unit. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. pull-up control is enabled in a bit unit. power source cnv ss input reference voltage analog power source table 6 pin description function except a port function a-d converter input pin interrupt input pin d-a converter input pin serial i/o3 function pin i/o port p4 interrupt input pin sub-clock generating i/o pin (resonator connected) interrupt input pin v cc , v ss cnv ss v ref av ss reset reset input clock input x in x out clock output p0 0 /an 8 p0 7 /an 15 i/o port p0 p1 0 /int 41 p1 1 /int 01 p1 2 p1 7 i/o port p1 p2 0 p2 7 i/o port p2 p3 0 /da 1 p3 1 /da 2 p3 2 , p3 3 p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 p4 0 /int 40 / x cout p4 1 /int 00 / x cin p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 p6 7 /an 7 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. pull-up control is enabled in a bit unit. serial i/o1 function pin serial i/o1, timer z function pin i/o port p5 i/o port p6 serial i/o2 function pin timer x function pin timer y function pin pwm output pin interrupt input pin a-d converter input pin i/o port p3
rev.3.02 nov 05, 2004 page 8 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. part numbering fig. 5 part numbering m3803 7 m 8 h xxx sp product name package type sp : 64p4b fp : 64p6n-a hp : 64p6q-a kp : 64p6u-a wg : 64f0g rom number omitted in the flash memory version. rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used as a user s rom area. however, they can be programmed or erased in the flash memory version, so that the users can use them. memory type m : mask rom version f : flash memory version ram size 0 1 2 3 4 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : standard omitted in the flash memory version. h : minner spec. change product : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes 9 a b c d e f 5 6 7 8 9 : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes
rev.3.02 nov 05, 2004 page 9 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. group expansion renesas plans to expand the 3803 group (spec. h) as follows. memory size flash memory size ......................................................... 60 k bytes mask rom size ................................................. 16 k to 60 k bytes ram size ............................................................ 640 to 2048 bytes packages 64p4b ......................................... 64-pin shrink plastic-molded dip 64p6n-a .................................... 0.8 mm-pitch plastic molded qfp 64p6q-a .................................. 0.5 mm-pitch plastic molded lqfp 64p6u-a .................................. 0.8 mm-pitch plastic molded lqfp 64f0g ...................................... 0.65 mm-pitch plastic molded lga fig. 6 memory expansion plan memory expansion plan 48k 32k 28k 24k 20k 16k 12k 8k 384 512 640 768 896 1024 60k 1152 1280 1408 1536 2048 3072 4032 rom size (bytes) ram size (bytes) M38039ffh M38039ff M38039mfh m38037m6h m38037m8h m38034m4h notes 1: products under development: the development schedule and specification may be revised without notice. 2: refer to ?803/3804 group data sheet?about 3803 group products other than 3803 group (spec. h) because there are electrical characteristics differences and so on. as of nov. 2004 : under development : mass production M38039mch
rev.3.02 nov 05, 2004 page 10 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. functional description central processing unit (cpu) the 3803 group (spec. h) uses the standard 740 family instruc- tion set. refer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for de- tails on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc. are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. fig.7 740 family cpu register structure [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 8. store registers other than those described in figure 7 with pro- gram when the user needs them during interrupts or subroutine calls (see table 7). [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
rev.3.02 nov 05, 2004 page 11 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 7 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 8 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r on-going routin e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s (pc l )m (s) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 (pc h )m (s) s u b r o u t i n e pop return address from stack p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i (ps) m (s) ( s ) ( s ) 1 ( s ) ( s ) + 1 interrupt service routine p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m (s) (pc h ) (s) (s) 1 m (s) (pc l ) ( s ) ( s ) 1 (pc l )m (s) (s) (s) + 1 ( s ) ( s ) + 1 (pc h )m (s) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) interrupt disable flag is 0
rev.3.02 nov 05, 2004 page 12 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can execute decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 8 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
rev.3.02 nov 05, 2004 page 13 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 9 structure of cpu mode register [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . c p u m o d e r e g i s t e r ( cpum : address 003b 16 ) b 7 b0 f i x t h i s b i t t o 1 . s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e 1
rev.3.02 nov 05, 2004 page 14 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. misrg (1) bit 0 of address 0010 16: oscillation stabilizing time set af- ter stp instruction released bit when the mcu stops the clock oscillation by the stp instruction and the stp instruction has been released by an external interrupt source, usually, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in order for the oscillation to stabilize. the user can inhibit the au- tomatic setting by setting 1 to bit 0 of misrg (address 0010 16 ). however, by setting this bit to 1 , the previous values, set just be- fore the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the stp instruction. figure 10 shows the structure of misrg. (2) bits 1, 2, 3 of address 0010 16: middle-speed mode auto- matic switch function in order to switch the clock mode of an mcu which has a sub- clock, the following procedure is necessary: set cpu mode register (003b 16 ) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). however, the 3803 group (spec. h) has the built-in function which automatically switches from low to middle-speed mode by pro- gram. middle-speed mode automatic switch by program the middle-speed mode can also be automatically switched by program while operating in low-speed mode. by setting the middle-speed automatic switch start bit (bit 3) of misrg (address 0010 16 ) to 1 in the condition that the middle-speed mode auto- matic switch set bit is 1 while operating in low-speed mode, the mcu will automatically switch to middle-speed mode. in this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of misrg (address 0010 16 ). fig. 10 structure of misrg misrg (misrg : address 0010 16 ) b7 b0 note: when automatic switch to middle-speed mode from low-speed mode occurs, the values of cpu mode register (3b 16 ) change. not used (return 0 when read) (do not write 1 to this bit) middle-speed mode automatic switch start bit (depending on program) 0: invalid 1: automatic switch start (note) middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles middle-speed mode automatic switch set bit 0: not set automatically 1: automatic switching enabled (note) oscillation stabilizing time set after stp instruction released bit 0: automatically set 01 16 to timer 1, ff 16 to prescaler 12 1: automatically set disabled
rev.3.02 nov 05, 2004 page 15 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. the reserved rom area can program/erase in the flash memory version. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 11 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0ff0 16 0fff 16 sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram size (bytes) address xxxx 16 rom size (bytes) address yyyy 16 reserved rom area address zzzz 16 sfr area not used
rev.3.02 nov 05, 2004 page 16 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 12 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 register (sio2) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator (brg1) serial i/o2 control register (sio2con) interrupt control register 2 (icon2) a-d conversion register 1 (ad1) prescaler y (prey) timer y (ty) ad/da control register (adcon) d-a1 conversion register (da1) d-a2 conversion register (da2) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm) a-d conversion register 2 (ad2) interrupt source selection register (intsel) watchdog timer control register (wdtcon) 0ff0 16 0ff1 16 port p0 pull-up control register (pull0) timer z low-order (tzl) timer z high-order (tzh) pwm control register (pwmcon) pwm prescaler (prepwm) timer z mode register (tzm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) port p1 pull-up control register (pull1) 0ff2 16 0ff3 16 port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) 0ff4 16 port p4 pull-up control register (pull4) 0ff5 16 0ff6 16 port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) reserved ? reserved ? reserved ? reserved ? reserved ? reserved ? reserved ? ? reserved area: do not write any data to these addresses, because these areas are reserved. 0fe0 16 0fe1 16 flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) 0fe2 16 0fe3 16 flash memory control register 2 (fmcr2) reserved ? 0fe4 16 reserved ? 0fe5 16 0fe6 16 reserved ? reserved ? 0fe7 16 0fe8 16 reserved ? reserved ? 0fe9 16 reserved ? 0fea 16 reserved ? 0feb 16 0fec 16 reserved ? reserved ? 0fed 16 0fee 16 reserved ? reserved ? 0fef 16 reserved ?
rev.3.02 nov 05, 2004 page 17 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- p0 0 /an 8 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 7 p2 0 /led 0 p2 7 /led 7 p3 0 /da 1 p3 1 /da 2 p3 2 p3 3 p3 4 /rxd 3 p3 5 /txd 3 p3 6 /s clk3 p3 7 /s rdy3 p4 0 /int 40 /x cin p4 1 /int 00 /x cout p4 2 /int 1 p4 3 /int 2 p4 4 /rxd 1 p4 5 /txd 1 p4 6 /s clk1 p4 7 /s rdy1 /cntr 2 pin name i/o structure cmos compatible input level cmos 3-state output non-port function ref.no. table 9 i/o port function related sfrs port p0 port p1 port p3 (1) (2) port p2 a-d converter input external interrupt input d-a converter output ad/da control register interrupt edge selection register ad/da control register (3) (4) (5) cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output port p4 serial i/o3 function i/o serial i/o3 control register uart3 control register (6) (7) (8) (9) external interrupt input sub-clock generating circuit external interrupt input serial i/o1 function i/o interrupt edge selection register cpu mode register interrupt edge selection register serial i/o1 control register uart1 control register (10) (11) (2) (6) (7) (8) (12) serial i/o1 function i/o timer z function i/o serial i/o1 control register timer z mode register serial i/o2 control register serial i/o2 function i/o port p5 port p6 (13) (14) (15) (16) (17) (18) (2) (1) timer x, y function i/o pwm output external interrupt input a-d converter input timer xy mode register pwm control register interrupt edge selection register ad/da control register notes 1 : refer to the applicable sections how to use double-function ports as function i/o ports. 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /pwm p5 7 /int 3 p6 0 /an 0 p6 7 /an 7 cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output
rev.3.02 nov 05, 2004 page 18 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 13 port block diagram (1) ( 6 ) p o r t s p 3 4 , p 4 4 s e r i a l i / o i n p u t ( 1 ) p o r t s p 0 , p 6 a - d c o n v e r t e r i n p u t analog input pin selection bit d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h p u l l - u p c o n t r o l b i t ( 2 ) p o r t s p 1 0 , p 1 1 , p 4 2 , p 4 3 , p 5 7 i n t e r r u p t i n p u t ( 3 ) p o r t s p 1 2 t o p 1 7 , p 2 ( 4 ) p o r t s p 3 0 , p 3 1 d a 1 o u t p u t e n a b l e ( p 3 0 ) d a 2 o u t p u t e n a b l e ( p 3 1 ) (8) ports p3 6 , p4 6 (7) ports p3 5 , p4 5 ( 5 ) p o r t s p 3 2 , p 3 3 d a t a b u s direction register p o r t l a t c h pull-up control bit p u l l - u p c o n t r o l b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d a t a b u s direction register p o r t l a t c h pull-up control bit d-a converter output d a t a b u s direction register p o r t l a t c h p u l l - u p c o n t r o l b i t serial i/o enable bit receive enable bit d i r e c t i o n r e g i s t e r port latch data bus direction register p o r t l a t c h d a t a b u s pull-up control bit s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t p-channel output disable bit s e r i a l i / o e n a b l e b i t s e r i a l i / o m o d e s e l e c t i o n b i t serial i/o enable bit s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t data bus d i r e c t i o n r e g i s t e r port latch p u l l - u p c o n t r o l b i t serial i/o external clock input s e r i a l i / o c l o c k o u t p u t serial i/o output
rev.3.02 nov 05, 2004 page 19 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 14 port block diagram (2) (10) port p4 0 (11) port p4 1 (13) port p5 0 port x c switch bit int 40 interrupt input port p4 1 serial i/o2 input (12) port p4 7 (9) port p3 7 s rdy3 output enable bit (14) port p5 1 int 00 interrupt input serial i/o3 enable bit serial i/o3 mode selection bit data bus direction register port latch pull-up control bit serial i/o3 ready output pull-up control bit data bus direction register port latch port x c switch bit oscillator cntr 2 interrupt input s rdy1 output enable bit serial i/o1 enable bit serial i/o1 mode selection bit data bus serial i/o1 ready output timer output data bus direction register port latch pull-up control bit sub-clock generating circuit input port x c switch bit pull-up control bit data bus direction register port latch pull-up control bit data bus direction register port latch serial i/o2 output serial i/o2 transmit completion signal serial i/o2 port selection bit p-channel output disable bit bit 2 timer z operating mode bits bit 1 bit 0 port latch direction register pull-up control bit
rev.3.02 nov 05, 2004 page 20 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 15 port block diagram (3) ( 1 6 ) p o r t p 5 3 ( 1 5 ) p o r t p 5 2 ( 1 7 ) p o r t s p 5 4 , p 5 5 ( 1 8 ) p o r t p 5 6 p w m o u t p u t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t d a t a b u s direction register p o r t l a t c h pull-up control bit s e r i a l i / o 2 e x t e r n a l c l o c k i n p u t s e r i a l i / o 2 c l o c k o u t p u t s rdy2 enable bit s e r i a l i / o 2 r e a d y o u t p u t data bus direction register p o r t l a t c h data bus direction register port latch p u l l - u p c o n t r o l b i t c n t r i n t e r r u p t i n p u t pulse output mode t i m e r o u t p u t d a t a b u s direction register port latch pwm output enable bit pull-up control bit pull-up control bit
rev.3.02 nov 05, 2004 page 21 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 16 structure of port pull-up control register (1) p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 0 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 0 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p b 7b 0 port p1 pull-up control register p 1 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 1 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p ( p u l l 1 : a d d r e s s 0 f f 1 1 6 ) ( p u l l 0 : a d d r e s s 0 f f 0 1 6 ) note : pull-up control is valid when the corresponding bit of the port direction register is 0 (input). when that bit is 1 (output), pull-up cannot be set to the port of which pull-up is selected. n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d .
rev.3.02 nov 05, 2004 page 22 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 17 structure of port pull-up control register (2) p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p2 0 pull-up control bit 0: no pull-up 1: pull-up p2 1 pull-up control bit 0: no pull-up 1: pull-up p2 2 pull-up control bit 0: no pull-up 1: pull-up p2 3 pull-up control bit 0: no pull-up 1: pull-up p2 4 pull-up control bit 0: no pull-up 1: pull-up p2 5 pull-up control bit 0: no pull-up 1: pull-up p2 6 pull-up control bit 0: no pull-up 1: pull-up p2 7 pull-up control bit 0: no pull-up 1: pull-up b7 b0 p o r t p 3 p u l l - u p c o n t r o l r e g i s t e r p3 0 pull-up control bit 0: no pull-up 1: pull-up p3 1 pull-up control bit 0: no pull-up 1: pull-up not used (return 0 when read) p3 4 pull-up control bit 0: no pull-up 1: pull-up p3 5 pull-up control bit 0: no pull-up 1: pull-up p3 6 pull-up control bit 0: no pull-up 1: pull-up p3 7 pull-up control bit 0: no pull-up 1: pull-up ( p u l l 3 : a d d r e s s 0 f f 3 1 6 ) ( p u l l 2 : a d d r e s s 0 f f 2 1 6 ) n o t e : p u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s 0 ( i n p u t ) . w h e n t h a t b i t i s 1 ( o u t p u t ) , p u l l - u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l - u p i s s e l e c t e d . note : pull-up control is valid when the corresponding bit of the port direction register is 0 (input). when that bit is 1 (output), pull-up cannot be set to the port of which pull-up is selected.
rev.3.02 nov 05, 2004 page 23 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 18 structure of port pull-up control register (3) port p4 pull-up control register b7 b0 p 4 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 4 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p b7 b0 p o r t p 5 p u l l - u p c o n t r o l r e g i s t e r p5 0 pull-up control bit 0: no pull-up 1: pull-up p5 1 pull-up control bit 0: no pull-up 1: pull-up p5 2 pull-up control bit 0: no pull-up 1: pull-up p5 3 pull-up control bit 0: no pull-up 1: pull-up p5 4 pull-up control bit 0: no pull-up 1: pull-up p5 5 pull-up control bit 0: no pull-up 1: pull-up p5 6 pull-up control bit 0: no pull-up 1: pull-up p5 7 pull-up control bit 0: no pull-up 1: pull-up ( p u l l 5 : a d d r e s s 0 f f 5 1 6 ) ( p u l l 4 : a d d r e s s 0 f f 4 1 6 ) note : pull-up control is valid when the corresponding bit of the port direction register is 0 (input). when that bit is 1 (output), pull-up cannot be set to the port of which pull-up is selected. note : pull-up control is valid when the corresponding bit of the port direction register is 0 (input). when that bit is 1 (output), pull-up cannot be set to the port of which pull-up is selected.
rev.3.02 nov 05, 2004 page 24 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 19 structure of port pull-up control register (4) p o r t p 6 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 p 6 0 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 1 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 2 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 3 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 4 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 5 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 6 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p p 6 7 p u l l - u p c o n t r o l b i t 0 : n o p u l l - u p 1 : p u l l - u p (pull6: address 0ff6 16 ) note : pull-up control is valid when the corresponding bit of the port direction register is 0 (input). when that bit is 1 (output), pull-up cannot be set to the port of which pull-up is selected.
rev.3.02 nov 05, 2004 page 25 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. interrupts the 3803 group (spaec. h) s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve in- ternal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the reset and the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts ex- cept the reset and the brk instruction interrupt. when several interrupt requests occur at the same time, the inter- rupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source selection which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 0039 16 ). 1. int 0 or timer z 2. cntr 1 or serial i/o3 reception 3. serial i/o2 or timer z 7. int 4 or cntr 2 8. a-d converter or serial i/o3 transmission external interrupt pin selection the occurrence sources of the external interrupt int 0 and int 4 can be selected from either input from int 00 and int 40 pin, or in- put from int 01 and int 41 pin by the int 0 , int 4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003a 16 ). notes when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer xy mode register (address 0023 16 ) timer z mode register (address 002a 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt source selection register (address 0039 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit or the interrupt source select bit to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. set the corresponding interrupt enable bit to 1 (enabled).
rev.3.02 nov 05, 2004 page 26 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. interrupt request generating conditions remarks interrupt source low fffc 16 fffa 16 high fffd 16 fffb 16 priority 1 2 table 10 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 timer z int 1 serial i/o1 reception serial i/o1 transmission at reset at detection of either rising or falling edge of int 0 input at timer z underflow at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmission shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of serial i/o3 data reception at completion of serial i/o2 data transmission or reception at timer z underflow at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at detection of either rising or falling edge of cntr 2 input at completion of a-d conversion at completion of serial i/o3 transmission shift or when transmission buffer is empty at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 3 4 5 6 7 8 9 10 timer x timer y timer 1 timer 2 cntr 0 cntr 1 serial i/o3 reception serial i/o2 timer z int 2 int 3 int 4 stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o3 is selected non-maskable software interrupt 11 ffe9 16 ffe8 16 12 cntr 2 a-d converter serial i/o3 transmission brk instruction 14 15 13 16 17 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16
rev.3.02 nov 05, 2004 page 27 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 20 interrupt control interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset
rev.3.02 nov 05, 2004 page 28 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 21 structure of interrupt-related registers i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r int 0 active edge selection bit int 1 active edge selection bit not used (returns 0 when read) int 2 active edge selection bit int 3 active edge selection bit int 4 active edge selection bit int 0 , int 4 interrupt switch bit 0 : int 00 , int 40 interrupt 1 : int 01 , int 41 interrupt not used (returns 0 when read) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 / t i m e r z i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 cntr 0 interrupt request bit cntr 1 /serial i/o3 receive interrupt request bit serial i/o2/timer z interrupt request bit int 2 interrupt request bit int 3 interrupt request bit int 4 /cntr 2 interrupt request bit ad converter/serial i/o3 transmit interrupt request bit not used (returns 0 when read) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) interrupt control register 2 0 : interrupts disabled 1 : interrupts enabled ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) 0 : falling edge active 1 : rising edge active 0 : falling edge active 1 : rising edge active cntr 0 interrupt enable bit cntr 1 /serial i/o3 receive interrupt enable bit serial i/o2/timer z interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit int 4 /cntr 2 interrupt enable bit ad converter/serial i/o3 transmit interrupt enable bit not used (returns 0 when read) i n t 0 / t i m e r z i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t b 7 i n t 0 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 0 i n t e r r u p t 1 : t i m e r z i n t e r r u p t s e r i a l i / o 2 / t i m e r z i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : s e r i a l i / o 2 i n t e r r u p t 1 : t i m e r z i n t e r r u p t n o t u s e d (d o n o t w r i t e 1 t o t h e s e b i t s . ) i n t 4 / c n t r 2 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t 4 i n t e r r u p t 1 : c n t r 2 i n t e r r u p t n o t u s e d ( d o n o t w r i t e 1 t o t h i s b i t . ) c n t r 1 / s e r i a l i / o 3 r e c e i v e i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : c n t r 1 i n t e r r u p t 1 : s e r i a l i / o 3 r e c e i v e i n t e r r u p t a d c o n v e r t e r / s e r i a l i / o 3 t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : a - d c o n v e r t e r i n t e r r u p t 1 : s e r i a l i / o 3 t r a n s m i t i n t e r r u p t i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( d o n o t w r i t e 1 t o t h e s e b i t s s i m u l t a n e o u s l y . ) (intsel: address 0039 16 ) b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b7 b0
rev.3.02 nov 05, 2004 page 29 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. timers 8-bit timers the 3803 group (spec. h) has four 8-bit timers: timer 1, timer 2, timer x, and timer y. the timer 1 and timer 2 use one prescaler in common, and the timer x and timer y use each prescaler. those are 8-bit prescalers. each of the timers and prescalers has a timer latch or a prescaler latch. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down-counters. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. when the timer underflows, the interrupt re- quest bit corresponding to that timer is set to 1 . timer divider the divider count source is switched by the main clock division ratio selection bits of cpu mode register (bits 7 and 6 at address 003b 16 ). when these bits are 00 (high-speed mode) or 01 (middle-speed mode), x in is selected. when these bits are 10 (low-speed mode), x cin is selected. prescaler 12 the prescaler 12 counts the output of the timer divider. the count source is selected by the timer 12, x count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(x in ) or f(x cin ). timer 1 and timer 2 the timer 1 and timer 2 counts the output of prescaler 12 and pe- riodically set the interrupt request bit. prescaler x and prescaler y the prescaler x and prescaler y count the output of the timer divider or f(x cin ). the count source is selected by the timer 12, x count source selection register (address 000e 16 ) and the timer y, z count source selection register (address 000f 16 ) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(x in ) or f(x cin ); and f(x cin ). timer x and timer y the timer x and timer y can each select one of four operating modes by setting the timer xy mode register (address 0023 16 ). (1) timer mode mode selection this mode can be selected by setting 00 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). explanation of operation the timer count operation is started by setting 0 to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). when the timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) pulse output mode mode selection this mode can be selected by setting 01 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). explanation of operation the operation is the same as the timer mode s. moreover the pulse which is inverted each time the timer underflows is output from cntr 0 /cntr 1 pin. regardless of the timer counting or not the output of cntr 0 /cntr 1 pin is initialized to the level of speci- fied by their active edge switch bits when writing to the timer. when the cntr 0 active edge switch bit (bit 2) and the cntr 1 ac- tive edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is 0 , the output starts with h level. when it is 1 , the output starts with l level. switching the cntr 0 or cntr 1 active edge switch bit will reverse the output level of the corresponding cntr 0 or cntr1 pin. precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to output in this mode.
rev.3.02 nov 05, 2004 page 30 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (3) event counter mode mode selection this mode can be selected by setting 10 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). explanation of operation the operation is the same as the timer mode s except that the timer counts signals input from the cntr 0 or cntr 1 pin. the valid edge for the count operation depends on the cntr 0 active edge switch bit (bit 2) or the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ). when it is 0 , the rising edge is valid. when it is 1 , the falling edge is valid. precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to input in this mode. (4) pulse width measurement mode mode selection this mode can be selected by setting 11 to the timer x operating mode bits (bits 1 and 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). explanation of operation when the cntr 0 active edge switch bit (bit 2) or the cntr 1 ac- tive edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is 1 , the timer counts during the term of one falling edge of cntr 0 /cntr 1 pin input until the next rising edge of input ( l term). when it is 0 , the timer counts during the term of one rising edge input until the next falling edge input ( h term). precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 / p5 5 to input in this mode. the count operation can be stopped by setting 1 to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). the interrupt request bit is set to 1 each time the timer underflows. ?recautions when switching count source when switching the count source by the timer 12, x and y count source selection bits, the value of timer count is altered in incon- siderable amount owing to generating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer.
rev.3.02 nov 05, 2004 page 31 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 22 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p 5 4 / c n t r 0 q q p5 5 /cntr 1 0 1 r r t t f(x cin ) f ( x c i n ) c l o c k f o r t i m e r 1 2 x i n x c i n ( 1 / 2 , 1 / 4 , 1 / 8 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 5 1 2 , 1 / 1 0 2 4 ) d i v i d e r c l o c k f o r t i m e r y c l o c k f o r t i m e r x c o u n t s o u r c e s e l e c t i o n b i t c n t r 0 a c t i v e e d g e s w i t c h b i t p o r t p 5 4 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e port p5 4 latch c n t r 0 a c t i v e e d g e s w i t c h b i t toggle flip-flop pulse width measurement mode timer mode pulse output mode t i m e r x c o u n t s t o p b i t p r e s c a l e r x ( 8 ) p r e s c a l e r x l a t c h ( 8 ) data bus t i m e r x l a t c h ( 8 ) t i m e r x ( 8 ) t o t i m e r x i n t e r r u p t r e q u e s t b i t t o c n t r 0 i n t e r r u p t r e q u e s t b i t t i m e r x l a t c h w r i t e p u l s e p u l s e o u t p u t m o d e clock for timer y c o u n t s o u r c e s e l e c t i o n b i t e v e n t c o u n t e r m o d e pulse width measurement mode timer mode pulse output mode t i m e r y c o u n t s t o p b i t e v e n t c o u n t e r m o d e 0 1 c n t r 1 a c t i v e e d g e s w i t c h b i t p r e s c a l e r y ( 8 ) prescaler y latch (8) d a t a b u s t i m e r y l a t c h ( 8 ) t i m e r y ( 8 ) t o t i m e r y i n t e r r u p t r e q u e s t b i t to cntr 1 interrupt request bit p o r t p 5 5 d i r e c t i o n r e g i s t e r pulse output mode p o r t p 5 5 l a t c h 1 0 c n t r 1 a c t i v e e d g e s w i t c h b i t toggle flip-flop timer y latch write pulse pulse output mode timer 2 latch (8) t i m e r 2 ( 8 ) t o t i m e r 2 i n t e r r u p t r e q u e s t b i t to timer 1 interrupt request bit c l o c k f o r t i m e r 1 2 prescaler 12 (8) prescaler 12 latch (8) data bus timer 1 latch (8) t i m e r 1 ( 8 ) 0 0 0 1 1 0 m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s
rev.3.02 nov 05, 2004 page 32 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 23 structure of timer xy mode register timer xy mode register (tm : address 0023 16 ) timer x operating mode bits b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : interrupt at falling edge count at rising edge in event counter mode 1 : interrupt at rising edge count at falling edge in event counter mode timer x count stop bit 0 : count start 1 : count stop timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 1 active edge switch bit 0 : interrupt at falling edge count at rising edge in event counter mode 1 : interrupt at rising edge count at falling edge in event counter mode timer y count stop bit 0 : count start 1 : count stop b 7 b0
rev.3.02 nov 05, 2004 page 33 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 24 structure of timer 12, x and timer y, z count source selection registers timer 12 count source selection bits b3b2b1b0 0000: f(x in )/2 or f(x cin )/2 0001: f(x in )/4 or f(x cin )/4 0010: f(x in )/8 or f(x cin )/8 0011: f(x in )/16 or f(x cin )/16 0100: f(x in )/32 or f(x cin )/32 0101: f(x in )/64 or f(x cin )/64 0110: f(x in )/128 or f(x cin )/128 0111: f(x in )/256 or f(x cin )/256 1000: f(x in )/512 or f(x cin )/512 1001: f ( x in ) /1024 or f ( x cin ) /1024 timer 12, x count source selection register (t12xcss : address 000e 16 ) b 7 b0 timer x count source selection bits b7b6b5b4 0000: f(x in )/2 or f(x cin )/2 1011 : 0001: f(x in )/4 or f(x cin )/4 1100 : 0010: f(x in )/8 or f(x cin )/8 1101 : not used 0011: f(x in )/16 or f(x cin )/16 1110 : 0100: f(x in )/32 or f(x cin )/32 1111 : 0101: f(x in )/64 or f(x cin )/64 0110: f(x in )/128 or f(x cin )/128 0111: f(x in )/256 or f(x cin )/256 1000: f(x in )/512 or f(x cin )/512 1001: f(x in )/1024 or f(x cin )/1024 1010: f ( x cin ) timer y, z count source selection register (tyzcss : address 000f 16 ) timer y count source selection bits b3b2b1b0 0000: f(x in )/2 or f(x cin )/2 0001: f(x in )/4 or f(x cin )/4 0010: f(x in )/8 or f(x cin )/8 0011: f(x in )/16 or f(x cin )/16 0100: f(x in )/32 or f(x cin )/32 0101: f(x in )/64 or f(x cin )/64 0110: f(x in )/128 or f(x cin )/128 0111: f(x in )/256 or f(x cin )/256 1000: f(x in )/512 or f(x cin )/512 1001: f(x in )/1024 or f(x cin )/1024 1010: f ( x cin ) b7 b0 timer z count source selection bits b7b6b5b4 0000: f(x in )/2 or f(x cin )/2 1011 : 0001: f(x in )/4 or f(x cin )/4 1100 : 0010: f(x in )/8 or f(x cin )/8 1101 : not used 0011: f(x in )/16 or f(x cin )/16 1110 : 0100: f(x in )/32 or f(x cin )/32 1111 : 0101: f(x in )/64 or f(x cin )/64 0110: f(x in )/128 or f(x cin )/128 0111: f(x in )/256 or f(x cin )/256 1000: f(x in )/512 or f(x cin )/512 1001: f(x in )/1024 or f(x cin )/1024 1010: f ( x cin ) 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : n ot use d 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : n o t u s e d
rev.3.02 nov 05, 2004 page 34 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. the timer z is a 16-bit timer. when the timer reaches 0000 16 , an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when the timer underflows, the interrupt request bit corresponding to the timer z is set to 1 . when reading/writing to the timer z, perform reading/writing to both the high-order byte and the low-order byte. when reading the timer z, read from the high-order byte first, followed by the low-or- der byte. do not perform the writing to the timer z between read operation of the high-order byte and read operation of the low-or- der byte. when writing to the timer z, write to the low-order byte first, followed by the high-order byte. do not perform the reading to the timer z between write operation of the low-order byte and write operation of the high-order byte. the timer z can select the count source by the timer z count source selection bits of timer y, z count source selection register (bits 7 to 4 at address 000f 16 ). timer z can select one of seven operating modes by setting the timer z mode register (address 002a 16 ). (1) timer mode this mode can be selected by setting 000 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. when an underflow occurs, the int 0 /timer z interrupt request bit (bit 0) of the interrupt request register 1 (address 003c 16 ) is set to 1 . during timer stop, usually write data to a latch and a timer at the same time to set the timer value. the timer count operation is started by setting 0 to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ). when the timer reaches 0000 16 , an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. when writing data to the timer during operation, the data is written only into the latch. then the new latch value is reloaded into the timer at the next underflow. (2) event counter mode this mode can be selected by setting 000 to the timer z operat- ing mode bits (bits 2 to 0) and setting 1 to the timer/event counter mode switch bit (bit 7) of the timer z mode register (ad- dress 002a 16 ). the valid edge for the count operation depends on the cntr 2 ac- tive edge switch bit (bit 5) of the timer z mode register (address 002a 16 ). when it is 0 , the rising edge is valid. when it is 1 , the falling edge is valid. the interrupt at an underflow is the same as the timer mode s. the operation is the same as the timer mode s. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. figure 27 shows the timing chart of the timer/event counter mode. (3) pulse output mode this mode can be selected by setting 001 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. the interrupt at an underflow is the same as the timer mode s. the operation is the same as the timer mode s. moreover the pulse which is inverted each time the timer underflows is output from cntr 2 pin. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 0 , the output starts with h level. when it is 1 , the output starts with l level. set the double-function port of cntr 2 pin and port p4 7 to output in this mode. the output from cntr 2 pin is initialized to the level depending on cntr 2 active edge switch bit by writing to the timer. when the value of the cntr 2 active edge switch bit is changed, the output level of cntr 2 pin is inverted. figure 28 shows the timing chart of the pulse output mode.
rev.3.02 nov 05, 2004 page 35 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (4) pulse period measurement mode this mode can be selected by setting 010 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. the interrupt at an underflow is the same as the timer mode s. when the pulse period measurement is completed, the int 4 / cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to 1 . the cycle of the pulse which is input from the cntr 2 pin is mea- sured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 0 , the timer counts during the term from one falling edge of cntr 2 pin input to the next fall- ing edge. when it is 1 , the timer counts during the term from one rising edge input to the next rising edge input. when the valid edge of measurement completion/start is detected, the 1 s complement of the timer value is written to the timer latch and ffff 16 is set to the timer. furthermore when the timer underflows, the timer z interrupt re- quest occurs and ffff 16 is set to the timer. when reading the timer z, the value of the timer latch (measured value) is read. the measured value is retained until the next measurement comple- tion. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse pe- riod). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during mea- surement. ffff 16 is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. conse- quently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. figure 29 shows the timing chart of the pulse period measurement mode. (5) pulse width measurement mode this mode can be selected by setting 011 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. the interrupt at an underflow is the same as the timer mode s. when the pulse widths measurement is completed, the int 4 / cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to 1 . the pulse width which is input from the cntr 2 pin is measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is 0 , the timer counts during the term from one rising edge input to the next falling edge input ( h term). when it is 1 , the timer counts during the term from one falling edge of cntr 2 pin input to the next rising edge of input ( l term). when the valid edge of measurement completion is detected, the 1 s complement of the timer value is written to the timer latch. when the valid edge of measurement completion/start is detected, ffff 16 is set to the timer. when the timer z underflows, the timer z interrupt occurs and ffff 16 is set to the timer z. when reading the timer z, the value of the timer latch (measured value) is read. the measured value is retained until the next measurement completion. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during mea- surement. ffff 16 is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. conse- quently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. figure 30 shows the timing chart of the pulse width measurement mode.
rev.3.02 nov 05, 2004 page 36 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (6) programmable waveform generating mode this mode can be selected by setting 100 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. the interrupt at an underflow is the same as the timer mode s. the operation is the same as the timer mode s. moreover the timer outputs the data set in the output level latch (bit 4) of the timer z mode register (address 002a 16 ) from the cntr 2 pin each time the timer underflows. changing the value of the output level latch and the timer latch af- ter an underflow makes it possible to output an optional waveform from the cntr 2 pin. set the double-function port of cntr 2 pin and port p4 7 to output in this mode. figure 31 shows the timing chart of the programmable waveform generating mode. (7) programmable one-shot generating mode this mode can be selected by setting 101 to the timer z operat- ing mode bits (bits 2 to 0) and setting 0 to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. the interrupt at an underflow is the same as the timer mode s. the trigger to generate one-shot pulse can be selected by the int 1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003a 16 ). when it is 0 , the falling edge active is selected; when it is 1 , the rising edge active is selected. when the valid edge of the int 1 pin is detected, the int 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003c 16 ) is set to 1 . h one-shot pulse; bit 5 of timer z mode register = 0 the output level of the cntr 2 pin is initialized to l at mode se- lection. when trigger generation (input signal to int 1 pin) is detected, h is output from the cntr 2 pin. when an underflow occurs, l is output. the h one-shot pulse width is set by the setting value to the timer z register low-order and high-order. when trigger generating is detected during timer count stop, al- though h is output from the cntr 2 pin, h output state contin- ues because an underflow does not occur. l one-shot pulse; bit 5 of timer z mode register = 1 the output level of the cntr 2 pin is initialized to h at mode se- lection. when trigger generation (input signal to int 1 pin) is detected, l is output from the cntr 2 pin. when an underflow occurs, h is output. the l one-shot pulse width is set by the setting value to the timer z low-order and high-order. when trigger generating is detected during timer count stop, although l is out- put from the cntr 2 pin, l output state continues because an underflow does not occur. set the double-function port of cntr 2 pin and port p4 7 to output, and of int 1 pin and port p4 2 to input in this mode. this mode cannot be used in low-speed mode. if the value of the cntr 2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from cntr 2 pin changes. figure 32 shows the timing chart of the programmable one-shot generating mode. which write control can be selected by the timer z write control bit (bit 3) of the timer z mode register (address 002a 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation writing data only to the latch is selected, the value is set to the timer latch by writing data to the address of timer z and the timer is updated at next underflow. after reset re- lease, the operation writing data to both the latch and the timer at the same time is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer z. in the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. a read-out of timer value is impossible in pulse period measure- ment mode and pulse width measurement mode. in the other modes, a read-out of timer value is possible regardless of count operating or stopped. however, a read-out of timer latch value is impossible. each interrupt active edge depends on setting of the cntr 2 ac- tive edge switch bit and the int 1 active edge selection bit. when switching the count source by the timer z count source se- lection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input sig- nals. therefore, select the timer count source before setting the value to the prescaler and the timer. to use the cntr 2 pin as normal i/o port p4 7 , set timer z operat- ing mode bits (b2, b1, b0) of timer z mode register (address 002a 16 ) to 000 .
rev.3.02 nov 05, 2004 page 37 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 25 block diagram of timer z 1 0 p4 2 /int 1 p4 7 /cntr 2 0 1 001 100 101 f(x cin ) x in x cin output level latch programmable one-shot generating mode programmable one-shot generating circuit cntr 2 active edge switch bit programmable one-shot generating mode data bus to timer z interrupt request bit to cntr 2 interrupt request bit to int 1 interrupt request bit programmable waveform generating mode pulse output mode cntr 2 active edge switch bit pulse output mode timer z low-order latch timer z low-order timer z high-order latch timer z high-order timer z operating mode bits port p4 7 direction register port p4 7 latch pulse period measurement mode pulse width measurement mode edge detection circuit timer z count stop bit count source selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) divider clock for timer z cntr 2 active edge switch bit d q t tq q s 1 0 0 1 timer/event counter mode switch bit
rev.3.02 nov 05, 2004 page 38 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 26 structure of timer z mode register t i m e r z m o d e r e g i s t e r ( t z m : a d d r e s s 0 0 2 a 1 6 ) timer z operating mode bits b2b1b0 0 0 0 : timer/event counter mode 0 0 1 : pulse output mode 0 1 0 : pulse period measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generating mode 1 0 1 : programmable one-shot generating mode 1 1 0 : not available 1 1 1 : not available timer z write control bit 0 : writing data to both latch and timer simultaneously 1 : writing data only to latch output level latch 0 : l output 1 : h output cntr 2 active edge switch bit 0 : event counter mode: count at rising edge pulse output mode: start outputting h pulse period measurement mode: measurement between two falling edges pulse width measurement mode: measurement of h term programmable one-shot generating mode: after start outputting l , h one-shot pulse generated interrupt at falling edge 1 : event counter mode: count at falling edge pulse output mode: start outputting l pulse period measurement mode: measurement between two rising edges pulse width measurement mode: measurement of l term programmable one-shot generating mode: after start outputting h , l one-shot pulse generated interrupt at rising edge timer z count stop bit 0 : count start 1 : count stop timer/event counter mode switch bit (note) 0 : timer mode 1 : event counter mode b 7 b0 note: when selecting the modes except the timer/event counter mode, set 0 to this bit.
rev.3.02 nov 05, 2004 page 39 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 27 timing chart of timer/event counter mode fig. 28 timing chart of pulse output mode f f f f 1 6 0 0 0 0 1 6 t l t r t r tr t l : v a l u e s e t t o t i m e r l a t c h t r : t i m e r i n t e r r u p t r e q u e s t ffff 16 0 0 0 0 1 6 tl tl : value set to timer latch tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = 0 ; falling edge active) tr tr tr tr w a v e f o r m o u t p u t f r o m c n t r 2 p i n cntr 2 cntr 2
rev.3.02 nov 05, 2004 page 40 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 29 timing chart of pulse period measurement mode (measuring term between two rising edges) fig. 30 timing chart of pulse width measurement mode (measuring l term) f f f f 1 6 0000 16 t 3 t rt r t2 t 1 cntr 2 c n t r 2 c n t r 2 c n t r 2 f f f f 1 6 + t 1 t 2 t 3 ffff 16 s i g n a l in p u t f r o m c n t r 2 p i n c n t r 2 o f r i s i n g e d g e a c t i v e t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t f f f f 1 6 0 0 0 0 1 6 t3 t r t2 t1 cntr 2 cntr 2 c n t r 2 ffff 16 + t2 t1 t3 c n t r 2 i n t e r r u p t o f r i s i n g e d g e a c t i v e ; m e a s u r e m e n t o f l w i d t h t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t s i g n a l i n p u t f r o m c n t r 2 p i n
rev.3.02 nov 05, 2004 page 41 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 31 timing chart of programmable waveform generating mode fig. 32 timing chart of programmable one-shot generating mode ( h one-shot pulse generating) f f f f 1 6 0 0 0 0 1 6 t3 t 2 t 1 t 2 t 3 l l t 1 t rtr t rt r c n t r 2 cntr 2 s i g n a l o u t p u t f r o m c n t r 2 p i n l : timer initial value tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = 0 ; falling edge active) f f f f 1 6 l l tr tr tr ll cntr 2 cntr 2 s i g n a l o u t p u t f r o m c n t r 2 p i n l : o n e - s h o t p u l s e w i d t h t r : t i m e r i n t e r r u p t r e q u e s t c n t r 2 : c n t r 2 i n t e r r u p t r e q u e s t ( c n t r 2 a c t i v e e d g e s w i t c h b i t = 0 ; f a l l i n g e d g e a c t i v e ) signal input from int 1 pin
rev.3.02 nov 05, 2004 page 42 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 33 block diagram of clock synchronous serial i/o1 fig. 34 operation of clock synchronous serial i/o1 1 / 4 1/4 f/f p 4 6 / s c l k 1 serial i/o1 status register s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 7 / s r d y 1 p 4 4 / r x d 1 p 4 5 / t x d 1 receive buffer register 1 address 0018 16 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) b a u d r a t e g e n e r a t o r 1 address 001c 16 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t falling-edge detector transmit buffer register 1 data bus a d d r e s s 0 0 1 8 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) transmit buffer empty flag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t address 0019 16 d a t a b u s a d d r e s s 0 0 1 a 1 6 transmit shift register 1 f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 tbe = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d 1 s e r i a l i n p u t r x d 1 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . r e c e i v e e n a b l e s i g n a l s r d y 1
rev.3.02 nov 05, 2004 page 43 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 35 block diagram of uart serial i/o1 fig. 36 operation of uart serial i/o1 f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register 1 address 0018 16 receive shift register 1 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register 1 data bus transmit shift register 1 address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart1 control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p4 6 /s clk1 serial i/o1 status register p4 4 /r x d 1 p4 5 /t x d 1 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changin g to tsc=0. notes ? ? serial output t x d 1 serial input r x d 1 receive buffer read signal
rev.3.02 nov 05, 2004 page 44 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart1 control register (uart1con)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the p4 5 /t x d 1 pin. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [transmit buffer register 1/receive buffer register 1 (tb1/rb1)] 0018 16 the transmit buffer register 1 and the receive buffer register 1 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.
rev.3.02 nov 05, 2004 page 45 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 37 structure of serial i/o1 control registers b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r serial i/o1 control register b 0 b0 brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as normal i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 to p4 7 operate as normal i/o pins) 1: serial i/o1 enabled (pins p4 4 to p4 7 operate as serial i/o pins) b7 u a r t 1 c o n t r o l r e g i s t e r character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 ) (sio1con : address 001a 16 ) (uart1con : address 001b 16 )
rev.3.02 nov 05, 2004 page 46 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. 2. notes when selecting clock asynchronous serial i/o 2.1 stop of transmission operation note clear the transmit enable bit to 0 (transmit disabled). the trans- mission operation does not stop by clearing the serial i/o1 enable bit to 0 . reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd1, rxd1, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd1 pin and an operation failure occurs. 2.2 stop of receive operation note clear the receive enable bit to 0 (receive disabled). 2.3 stop of transmit/receive operation note 1 (only transmission operation is stopped) clear the transmit enable bit to 0 (transmit disabled). the trans- mission operation does not stop by clearing the serial i/o1 enable bit to 0 . reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd 1 , rxd 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd 1 pin and an operation failure occurs. note 2 (only receive operation is stopped) clear the receive enable bit to 0 (receive disabled). clear the serial i/o1 enable bit and the transmit enable bit to 0 (serial i/o and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd1, rxd1, s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to 1 at this time, the data during internally shifting is output to the txd1 pin and an operation failure occurs. 1.2 stop of receive operation note clear the receive enable bit to 0 (receive disabled), or clear the serial i/o1 enable bit to 0 (serial i/o disabled). 1.3 stop of transmit/receive operation note clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception can- not be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also oper- ates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clear- ing the serial i/o1 enable bit to 0 (serial i/o disabled) (refer to 1.1 ).
rev.3.02 nov 05, 2004 page 47 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. 3. s rdy1 output of reception side note when signals are output from the s rdy1 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to 1 (transmit enabled). 4. setting serial i/o1 control register again note set the serial i/o1 control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to 0. 5. data transmission control with referring to transmit shift register completion flag note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is con- trolled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk1 input level. also, write data to the transmit buffer register at h of the s clk1 input level. 7. transmit interrupt request when transmit enable bit is set note when using the transmit interrupt, take the following sequence. ? set the serial i/o1 transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o1 transmit interrupt request bit to 0 after 1 or more instruction has executed. ? set the serial i/o1 transmit interrupt enable bit to 1 (enabled). reason when the transmit enable bit is set to 1 , the transmit buffer empty flag and the transmit shift register shift completion flag are also set to 1 . therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to 1 can be set with the ldm instruction at the same time
rev.3.02 nov 05, 2004 page 48 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register. [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains eight bits which control various serial i/o2 functions. fig. 38 structure of serial i/o2 control register fig. 39 block diagram of serial i/o2 s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n : a d d r e s s 0 0 1 d 1 6 ) b 7 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 0 0 0 : f ( x i n ) / 8 ( f ( x c i n ) / 8 i n l o w - s p e e d m o d e ) 0 0 1 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 0 1 0 : f ( x i n ) / 3 2 ( f ( x c i n ) / 3 2 i n l o w - s p e e d m o d e ) 0 1 1 : f ( x i n ) / 6 4 ( f ( x c i n ) / 6 4 i n l o w - s p e e d m o d e ) 1 1 0 : f ( x i n ) / 1 2 8 ( f ( x c i n ) / 1 2 8 i n l o w - s p e e d m o d e ) 1 1 1 : f ( x i n ) / 2 5 6 ( f ( x c i n ) / 2 5 6 i n l o w - s p e e d m o d e ) s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 s i g n a l o u t p u t s r d y 2 o u t p u t e n a b l e b i t 0 : i / o p o r t 1 : s r d y 2 s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k p 5 1 / s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) b 0 b 2 b 1 b 0 1 0 0 1 0 1 s r d y 2 s c l k 2 0 1 1 / 8 1 / 1 6 1 / 3 2 1/64 1/128 1/256 d a t a b u s serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o2 register (8) synchronization circuit serial i/o2 port selection bit s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s r d y 2 o u t p u t e n a b l e b i t e x t e r n a l c l o c k i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s d i v i d e r p 5 2 / s c l k 2 p 5 1 / s o u t 2 p 5 0 / s i n 2 p 5 2 l a t c h p 5 1 l a t c h p 5 3 l a t c h p 5 3 / s r d y 2 f(x in ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) address 001f 16
rev.3.02 nov 05, 2004 page 49 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 40 timing of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 t r a n s f e r c l o c k ( n o t e 1 ) s e r i a l i / o 2 o u t p u t s o u t 2 s e r i a l i / o 2 i n p u t s i n 2 r e c e i v e e n a b l e s i g n a l s r d y 2 s e r i a l i / o 2 r e g i s t e r w r i t e s i g n a l ( n o t e 2 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t s e t 1: when the internal clock is selected as the transfer clock, the divide ratio of f(x in ), or f(x cin ) in low-speed mode, can be selected by setting bits 0 to 2 of the serial i/o2 control register. 2: when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion. n o t e s
rev.3.02 nov 05, 2004 page 50 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. serial i/o3 serial i/o3 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o3 mode can be selected by setting the serial i/o3 mode selection bit of the serial i/o3 control register (bit 6 of address 0032 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 41 block diagram of clock synchronous serial i/o3 fig. 42 operation of clock synchronous serial i/o3 1 / 4 1/4 f/f p 3 6 / s c l k 3 serial i/o3 status register s e r i a l i / o 3 c o n t r o l r e g i s t e r p 3 7 / s r d y 3 p 3 4 / r x d 3 p 3 5 / t x d 3 receive buffer register 3 address 0030 16 r e c e i v e s h i f t r e g i s t e r 3 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) clock control circui t s h i f t c l o c k serial i/o3 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator 3 address 002f 16 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t falling-edge detector transmit buffer register 3 data bus a d d r e s s 0 0 3 0 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) transmit buffer empty flag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t address 0031 16 d a t a b u s a d d r e s s 0 0 3 2 1 6 transmit shift register 3 f ( x i n ) ( f ( x c i n ) i n l o w - s p e e d m o d e ) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 tbe = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d 3 s e r i a l i n p u t r x d 3 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 3 0 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 3 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 3
rev.3.02 nov 05, 2004 page 51 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o3 mode selection bit of the serial i/o3 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 43 block diagram of uart serial i/o3 fig. 44 operation of uart serial i/o3 f ( x i n ) 1/4 o e p ef e 1 / 1 6 1 / 1 6 d a t a b u s receive buffer register 3 a d d r e s s 0 0 3 0 1 6 receive shift register 3 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) baud rate generator 3 frequency division ratio 1/(n+1) a d d r e s s 0 0 2 f 1 6 st/sp/pa generator transmit buffer register 3 data bus transmit shift register 3 address 0030 16 transmit shift completion flag (tsc) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) transmit interrupt request (ti) a d d r e s s 0 0 3 1 1 6 s t d e t e c t o r s p d e t e c t o r u a r t 3 c o n t r o l r e g i s t e r a d d r e s s 0 0 3 3 1 6 character length selection bit address 0032 16 brg count source selection bit transmit interrupt source selection bit serial i/o3 synchronous clock selection bit c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s serial i/o3 control register p 3 6 / s c l k 3 s e r i a l i / o 3 s t a t u s r e g i s t e r p 3 4 / r x d 3 p 3 5 / t x d 3 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o3 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changin g to tsc=0. notes ? ? serial output t x d 3 serial input r x d 3 receive buffer read signal
rev.3.02 nov 05, 2004 page 52 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. [serial i/o3 control register (sio3con)] 0032 16 the serial i/o3 control register consists of eight control bits for the serial i/o3 function. [uart3 control register (uart3con)] 0033 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the p3 5 /t x d 3 pin. [serial i/o3 status register (sio3sts)] 0031 16 the read-only serial i/o3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o3 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o3 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o3 enable bit sioe (bit 7 of the serial i/o3 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o3 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o3 control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [transmit buffer register 3/receive buffer register 3 (tb3/rb3)] 0030 16 the transmit buffer register 3 and the receive buffer register 3 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [baud rate generator 3 (brg3)] 002f 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.
rev.3.02 nov 05, 2004 page 53 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 45 structure of serial i/o3 control registers b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 3 s t a t u s r e g i s t e r serial i/o3 control register b 0 b0 brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o3 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy3 output enable bit (srdy) 0: p3 7 pin operates as normal i/o pin 1: p3 7 pin operates as s rdy3 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o3 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o3 enable bit (sioe) 0: serial i/o disabled (pins p3 4 to p3 7 operate as normal i/o pins) 1: serial i/o enabled (pins p3 4 to p3 7 operate as serial i/o pins) b7 u a r t 3 c o n t r o l r e g i s t e r character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p3 5 /t x d 3 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 ( s i o 3 s t s : a d d r e s s 0 0 3 1 1 6 ) (sio3con : address 0032 16 ) (uart3con : address 0033 16 )
rev.3.02 nov 05, 2004 page 54 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. 2. notes when selecting clock asynchronous serial i/o 2.1 stop of transmission operation note clear the transmit enable bit to 0 (transmit disabled). the trans- mission operation does not stop by clearing the serial i/o3 enable bit to 0 . reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd 3 , rxd 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o3 enable bit is set to 1 at this time, the data during internally shifting is output to the txd 3 pin and an operation failure occurs. 2.2 stop of receive operation note clear the receive enable bit to 0 (receive disabled). 2.3 stop of transmit/receive operation note 1 (only transmission operation is stopped) clear the transmit enable bit to 0 (transmit disabled). the trans- mission operation does not stop by clearing the serial i/o3 enable bit to 0 . reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd 3 , rxd 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o3 enable bit is set to 1 at this time, the data during internally shifting is output to the txd 3 pin and an operation failure occurs. note 2 (only receive operation is stopped) clear the receive enable bit to 0 (receive disabled). clear the serial i/o3 enable bit and the transmit enable bit to 0 (serial i/o and transmit disabled). reason since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd 3 , rxd 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd 3 pin and an operation failure occurs. 1.2 stop of receive operation note clear the receive enable bit to 0 (receive disabled), or clear the serial i/o3 enable bit to 0 (serial i/o disabled). 1.3 stop of transmit/receive operation note clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception can- not be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also oper- ates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clear- ing the serial i/o3 enable bit to 0 (serial i/o disabled) (refer to 1.1 ).
rev.3.02 nov 05, 2004 page 55 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. 3. s rdy3 output of reception side note when signals are output from the s rdy3 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy3 output enable bit, and the transmit enable bit to 1 (transmit enabled). 4. setting serial i/o3 control register again note set the serial i/o3 control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to 0. 5. data transmission control with referring to transmit shift register completion flag note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when data transmission is con- trolled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h of the s clk3 input level. also, write data to the transmit buffer register at h of the s clk input level. 7. transmit interrupt request when transmit enable bit is set note when using the transmit interrupt, take the following sequence. ? set the serial i/o3 transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o3 transmit interrupt request bit to 0 after 1 or more instruction has executed. ? set the serial i/o3 transmit interrupt enable bit to 1 (enabled). reason when the transmit enable bit is set to 1 , the transmit buffer empty flag and the transmit shift register shift completion flag are also set to 1 . therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o3 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to 1 can be set with the ldm instruction at the same time
rev.3.02 nov 05, 2004 page 56 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pulse width modulation (pwm) the 3803 group (spec. h) has pwm functions with an 8-bit reso- lution, based on a signal that is the clock input x in or that clock input divided by 2 or the clock input x cin or that clock input di- vided by 2 in low-speed mode. data setting the pwm output pin also functions as port p5 6 . set the pwm pe- riod by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 ? (n+1) / f(x in ) = 31.875 ? (n+1) s (when f(x in ) = 8 mhz) output pulse h term = pwm period ? m / 255 = 0.125 ? (n+1) ? m s (when f(x in ) = 8 mhz) fig. 46 timing of pwm period fig. 47 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1 , operation starts by initializing the pwm output circuit, and pulses are output starting at an h . if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 3 1 . 8 7 5 ? m ? ( n + 1 ) 255 s t = [ 3 1 . 8 7 5 ? ( n + 1 ) ] s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source is f(x in )) data bus count source selection bit 0 1 pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1 / 2 x i n o r x c i n port p5 6 latch p w m e n a b l e b i t p o r t p 5 6 p w m p r e s c a l e r
rev.3.02 nov 05, 2004 page 57 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 48 structure of pwm control register fig. 49 pwm output timing when pwm register or pwm prescaler is changed p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 2b 1 6 ) p w m f u n c t i o n e n a b l e b i t c o u n t s o u r c e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0 0 : p w m d i s a b l e d 1 : p w m e n a b l e d 0 : f ( x i n ) 1 : f ( x i n ) / 2 a b c b t c t2 = pwm output pwm register write signal pwm prescaler write signal (changes h term from a to b .) (changes pwm period from t to t2 .) when the contents of the pwm register or pwm prescaler have changed, the pwm out p ut will chan g e from the next p eriod after the chan g e. t t t2
rev.3.02 nov 05, 2004 page 58 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter [a-d conversion register 1, 2 (ad1, ad2)] 0035 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 is the conversion mode se- lection bit. when this bit is set to 0, the a-d converter becomes the 10-bit a-d mode. when this bit is set to 1, that becomes the 8-bit a-d mode. the conversion result of the 8-bit a-d mode is stored in the a-d conversion register 1. as for 10-bit a-d mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading pro- cedure of the a-d conversion registers 1, 2 after a-d conversion is completed (in figure 51). as for 10-bit a-d mode, the 8-bit reading inclined to msb is per- formed when reading the a-d converter register 1 after a-d conversion is started; and when the a-d converter register 1 is read after reading the a-d converter register 2, the 8-bit reading inclined to lsb is performed. [ad/da control register (adcon)] 0034 16 the ad/da control register controls the a-d conversion process. bits 0 to 2 and bit 4 select a specific analog input pin. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between v ref and av ss into 1024, and that outputs the comparison voltage in the 10-bit a-d mode (256 division in 8-bit a-d mode). the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref voltage (see below), with the input voltage. 10-bit a-d mode (10-bit reading) v ref = ? n (n = 0 1023) 10-bit a-d mode (8-bit reading) v ref = ? n (n = 0 255) 8-bit a-d mode v ref = ? (n 0.5) (n = 1 255) =0 (n = 0) fig. 50 structure of ad/da control register channel selector the channel selector selects one of ports p6 7 /an 7 to p6 0 /an 0 or p0 7 /an 15 to p0 0 /an 8 , and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. v ref 256 v ref 256 fig. 51 structure of 10-bit a-d mode reading v ref 1024 a d / d a c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s 1 0 0 0 : p 6 0 / a n 0 o r p 0 0 / a n 8 0 0 1 : p 6 1 / a n 1 o r p 0 1 / a n 9 0 1 0 : p 6 2 / a n 2 o r p 0 2 / a n 1 0 0 1 1 : p 6 3 / a n 3 o r p 0 3 / a n 1 1 1 0 0 : p 6 4 / a n 4 o r p 0 4 / a n 1 2 1 0 1 : p 6 5 / a n 5 o r p 0 5 / a n 1 3 1 1 0 : p 6 6 / a n 6 o r p 0 6 / a n 1 4 1 1 1 : p 6 7 / a n 7 o r p 0 7 / a n 1 5 a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t 2 0 : a n 0 t o a n 7 s i d e 1 : a n 8 t o a n 1 5 s i d e n o t u s e d ( r e t u r n s 0 w h e n r e a d ) d a 1 o u t p u t e n a b l e b i t 0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d d a 2 o u t p u t e n a b l e b i t 0 : d a 2 o u t p u t d i s a b l e d 1 : d a 2 o u t p u t e n a b l e d b 7 b 0 b 2 b 1 b 0 10-bit reading (read address 0038 16 before 0035 16 ) a-d conversion register 2 (ad2: address 0038 16 ) a-d conversion register 1 (ad1: address 0035 16 ) 8-bit reading (read only address 0035 16 ) a-d conversion register 1 (ad1: address 0035 16 ) note : bits 2 to 6 of address 0038 16 become 0 at reading. b 8 b 7 b 6 b 5 b4 b3 b 2 b1 b0 b7 b 0 b 9 b 7 b 0 b 9 b 8 b 7 b 6b 5b 4 b 3 b 2 b 7 b 0 0
rev.3.02 nov 05, 2004 page 59 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 52 block diagram of a-d converter c h a n n e l s e l e c t o r a - d c o n t r o l c i r c u i t a - d c o n v e r s i o n r e g i s t e r 1 r e s i s t o r l a d d e r v ref av ss c o m p a r a t o r a d c o n v e r t e r i n t e r r u p t r e q u e s t b7 b0 4 10 p 6 0 / a n 0 p 6 1 / a n 1 p 6 2 / a n 2 p 6 3 / a n 3 p 6 4 / a n 4 d a t a b u s a d / d a c o n t r o l r e g i s t e r a - d c o n v e r s i o n r e g i s t e r 2 ( a d d r e s s 0 0 3 4 1 6 ) ( a d d r e s s 0 0 3 8 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) p 6 5 / a n 5 p 6 6 / a n 6 p6 7 /an 7 p0 0 /an 8 p0 1 /an 9 p 0 2 / a n 1 0 p 0 3 / a n 1 1 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15
rev.3.02 nov 05, 2004 page 60 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. d-a converter the 3803 group (spec. h) has two internal d-a converters (da1 and da2) with 8-bit resolution. the d-a conversion is performed by setting the value in each d-a conversion register. the result of d-a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to 1 . when using the d-a converter, the corresponding port direction register bit (p3 0 /da 1 or p3 1 /da 2 ) must be set to 0 (input status). the output analog voltage v is determined by the value n (decimal notation) in the d-a conversion register as follows: v = v ref ? n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , and the da output enable bits are cleared to 0 , and the p3 0 /da 1 and p3 1 /da 2 pins become high impedance. the da output does not have buffers. accordingly, connect an ex- ternal buffer when driving a low-impedance load. fig. 53 block diagram of d-a converter fig. 54 equivalent connection circuit of d-a converter (da1) p 3 0 / d a 1 d - a 1 c o n v e r s i o n r e g i s t e r ( 8 ) r-2r resistor ladder d a 1 o u t p u t e n a b l e b i t p 3 1 / d a 2 d - a 2 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 2 o u t p u t e n a b l e b i t d a t a b u s av ss v r e f 0 1 msb 0 1 r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r r 2 r2 r lsb 2r p3 0 /da 1 d-a1 conversion register da 1 output enable bit
rev.3.02 nov 05, 2004 page 61 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ff 16 is set when watchdog timer control register is written to. reset release time waiting watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. watchdog timer initial value watchdog timer l is set to ff 16 and watchdog timer h is set to ff 16 by writing to the watchdog timer control register (address 001e 16 ) or at a reset. any write instruction that causes a write sig- nal can be used, such as the sta, ldm, clb, etc. data can only be written to bits 6 and 7 of the watchdog timer control register. regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. watchdog timer operations the watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. an internal reset occurs when watchdog timer h underflows. the reset is released after its release time. after the release, the program is restarted from the reset vector address. usually, write to the watchdog timer control register by software before an underflow of the watchdog timer h. the watchdog timer does not function if the watchdog timer control register is not written to at least once. fig. 56 structure of watchdog timer control register when bit 6 of the watchdog timer control register is kept at 0 , the stp instruction is enabled. when that is executed, both the clock and the watchdog timer stop. count re-starts at the same time as the release of stop mode (note) . the watchdog timer does not stop while a wit instruction is executed. in addition, the stp in- struction is disabled by writing 1 to this bit again. when the stp instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. once a 1 is written to this bit, it cannot be programmed to 0 again. the following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer h. bit 7 of the watchdog timer control register is 0 : when x cin = 32.768 khz; 32 s when x in = 16 mhz; 65.536 ms bit 7 of the watchdog timer control register is 1 : when x cin = 32.768 khz; 125 ms when x in = 16 mhz; 256 s note: the watchdog timer continues to count even while waiting for a stop release. therefore, make sure that watchdog timer h does not un- derflow during this period. fig. 55 block diagram of watchdog timer b 7 watchdog timer h (for read-out of high-order 6 bit) stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer control register (wdtcon : address 001e 16 ) b 0
rev.3.02 nov 05, 2004 page 62 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. reset circuit to reset the microcomputer, reset pin should be held at an ? level for 16 cycles or more of x in . then the reset pin is returned to an ??level (the power source voltage should be between 1.8 v and 5.5 v (between 2.7 v to 5.5 v for flash memory version), and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage for the mask rom version is less than 0.29 v for v cc of 1.8 v. in the flash memory version, input to the reset pin in the follow- ing procedure. when power source is stabilized (1) input ??level to reset pin. (2) input ??level for 16 cycles or more to x in pin. (3) input ??level to reset pin. at power-on (1) input ??level to reset pin. (2) increase the power source voltage to 2.7 v. (3) wait for td(p-r) until internal power source has stabilized. (4) input ??level for 16 cycles or more to x in pin. (5) input ??level to reset pin. fig. 58 reset sequence fig. 57 reset circuit example reset internal reset data address sync x in : 10.5 to 18.5 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( ) is f(x in )=8 f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from the vector table. notes v cc reset v cc reset example at v cc = 5v note 1: reset release voltage mask rom version: vcc = 1.8 v flash memory version: vcc = 2.7 v 2: in the flash memor y version , this time is re q uired td ( p-r ) +x in 16 c y cles or more. (note 2) (note 1) 0.2v cc or less 0v 0v v cc reset 0v 0v v cc reset td(p-r)+x in 16 cycles or more 5v 5v 2.7 v power source voltage detection circuit
rev.3.02 nov 05, 2004 page 63 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 59 internal status at reset timer z (low-order) (tzl) timer z (high-order) (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) ad/da control register (adcon) a-d conversion register 1 (ad1) d-a1 conversion register (da1) d-a2 conversion register (da2) a-d conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) port p0 pull-up control register (pull0) port p1 pull-up control register (pull1) port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) port p4 pull-up control register (pull4) port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) processor status register program counter xxxxxxxx 1110 0 0 00 note : x : not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) register contents 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0fe0 16 0fe1 16 0fe2 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 (ps) (pc h ) (pc l ) address ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 ff 16 00 16 ff 16 ff 16 ff 16 ff 16 xxxxxxxx 00111111 xxxxxxxx 1 fffd 16 contents fffc 16 contents xx xx xx x port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) 00110011 00110011 xxxxxxxx 10000000 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10000000 11 100000 00 001000 xx 000000 01 00 1000 00 00 0001 01 00 0000 01 00 0101
rev.3.02 nov 05, 2004 page 64 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. clock generating circuit the 3803 group (spec. h) has two built-in oscillation circuits: main clock x in -x out oscillation circuit and sub clock x cin -x cout oscil- lation circuit. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the cir- cuit constants in accordance with the resonator manufacturer s recommended values. no external resistor is needed between xin and xout since a feed-back resistor exists on-chip.(an external feed-back resistor may be needed depending on conditions.) however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after re- set is released, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set sufficient time for oscillation to stabilize. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. after stp instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the stp in- struction, and the output of the prescaler 12 is connected to timer 1. set the timer 1 interrupt enable bit to disabled ( 0 ) before ex- ecuting the stp instruction. oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the cpu (remains at h ) until timer 1 underflows. the internal clock is supplied for the first time, when timer 1 underflows. therefore make sure not to set the timer 1 interrupt request bit to 1 before the stp instruction stops the oscillator. when the oscillator is re- started by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. with the flash memory version, the internal power supply circuit is changed to low power consumption mode for consumption current reduction at the time of stp instruction execution. although an internal power supply circuit is usually changed to the normal operation mode at the time of the return from an stp in- struction, since a certain time is required to start the power supply to the flash memory and operation of flash memory to be enabled, set wait time 100 s or more with the flash memory version by the oscillation stabilization time set function after release of the stp instruction which used the timer 1. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3f(x cin ). when using the quartz-crystal oscillator of high frequency, such as 16 mhz etc., it may be necessary to select a specific oscillator with the specification demanded.
rev.3.02 nov 05, 2004 page 65 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 60 ceramic resonator circuit fig. 61 external clock input circuit v cc v ss x cin x cout x in x out open open external oscillation circuit external oscillation circuit v cc v ss x c i n x c o u t x i n x o u t c i n c o u t c c i n c c o u t r f r d rd (note) n o t e s : i n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . t h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g . u s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r . a l s o , i f t h e o s c i l l a t o r m a n u f a c t u r e r ' s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p t h o u g h a f e e d b a c k r e s i s t o r e x i s t s o n - c h i p , i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n x i n a n d x o u t f o l l o w i n g t h e i n s t r u c t i o n .
rev.3.02 nov 05, 2004 page 66 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. wit instruction stp instruction timing (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l port x c switch bit ? ? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) notes 1: either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b4) to 1 . 2: f(x in )/16 is supplied as the count source to the prescaler 12 at reset. the count source before executing the stp instruction is supplied as the count source at executing stp instruction. 3: when bit 0 of misrg is 0 , timer 1 is set 01 16 and prescaler 12 is set ff 16 automatically. when bit 0 of misrg is 1 , set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. main clock division ratio selection bits (note 1) prescaler 12 timer 1 reset or stp instruction (note 2) divider (note 3) reset (note 4) fig. 62 system clock generating circuit block diagram
rev.3.02 nov 05, 2004 page 67 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 63 state transitions of system clock cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0 : operating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 0 0 : = f(x in )/2 ( high-speed mode) 0 1 : = f(x in )/8 (middle-speed mode) 1 0 : = f(x cin )/2 (low-speed mode) 1 1 : not available note s r e s e t c m 4 1 0 c m 4 0 1 c m 6 1 0 c m 4 1 0 c m 6 1 0 c m 7 1 0 c m 4 1 0 c m 5 1 0 cm 6 1 0 c m 6 1 0 cpu mode register b7 b4 c m 7 0 1 c m 6 1 0 (cpum : address 003b 16 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) cm 7 =0 cm 6 =1 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) c m 7 = 1 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) c m 7 = 1 c m 6 = 0 c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) low-speed mode (f( )=16 khz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y c o n n e c t i n g p r e s c a l e r 1 2 a n d t i m e r 1 i n m i d d l e / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s b y t i m e r 1 a n d t i m e r 2 i n l o w - s p e e d m o d e . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k .
rev.3.02 nov 05, 2004 page 68 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 11 summary of 3803 group (spec. h) s flash memory version flash memory mode the 3803 group (spec. h) s flash memory version has the flash memory that can be rewritten with a single power source. for this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). this flash memory version has some blocks on the flash memory as shown in figure 64 and each block can be erased. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user s application sys- tem. this boot rom area can be rewritten in only parallel i/o mode. table 11 lists the summary of the 3803 group (spec. h) flash memory version. item power source voltage (vcc) program/erase v pp voltage (v pp ) flash memory mode erase block division user rom area/data rom area boot rom area (note) program method erase method program/erase control method number of commands number of program/erase times rom code protection specifications v cc = 2.7 to 5.5 v v cc = 2.7 to 5.5 v 3 modes; parallel i/o mode, standard serial i/o mode, cpu rewrite mode refer to fig. 64. not divided (4k bytes) in units of bytes block erase program/erase control by software command 5 commands 100 available in parallel i/o mode and standard serial i/o mode note : the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be erased and written in only parallel i/o mode.
rev.3.02 nov 05, 2004 page 69 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 64 block diagram of built-in flash memory the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the stan- dard serial i/o mode becomes unusable.) see figure 64 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset and the cnv ss pin high after pulling the p4 5 /txd 1 pin and cnvss pin high, the cpu starts op- erating (start address of program is stored into addresses fffc 16 and fffd 16 ) using the control program in the boot rom area. this mode is called the boot mode . also, user rom area can be rewritten using the control program in the boot rom area. block addresses refer to the maximum address of each block. these addresses are used in the block erase command. in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 64 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area before it can be executed. sfr area internal ram area (2k bytes) 0000 16 0040 16 083f 16 sfr area internal flash memory area (60k bytes) 0fe0 16 ram ffff 16 0fff 16 1000 16 user rom area data block b: 2k bytes 1000 16 1800 16 e000 16 c000 16 ffff 16 f000 16 ffff 16 boot rom area 4k bytes notes 1: the boot rom area can be rewritten in a paral- lel i/o mode. (access to except boot rom area is disablrd.) 2: to specify a block, use the maximum address in the block. block 3: 24k bytes 2000 16 8000 16 data block a: 2k bytes block 2: 16k bytes block 1: 8 k bytes block 0: 8 k bytes
rev.3.02 nov 05, 2004 page 70 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. cpu rewrite mode is usable in the single-chip or boot mode. the only user rom area can be rewritten. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory as instructed by software commands. this rewrite control program must be transferred to internal ram area before it can be executed. the mcu enters cpu rewrite mode by setting 1 to the cpu re- write mode select bit (bit 1 of address 0fe0 16 ). then, software commands can be accepted. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 65 shows the flash memory control register 0. bit 0 of the flash memory control register 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is 0 (busy). otherwise, it is 1 (ready). bit 1 of the flash memory control register 0 is the cpu rewrite mode select bit. when this bit is set to 1 , the mcu enters cpu rewrite mode. and then, software commands can be accepted. in cpu rewrite mode, the cpu becomes unable to access the inter- nal flash memory directly. therefore, use the control program in the internal ram for write to bit 1. to set this bit 1 to 1 , it is nec- essary to write 0 and then write 1 in succession to bit 1. the bit can be set to 0 by only writing 0 . bit 2 of the flash memory control register 0 is the 8 kb user block e/w enable bit. by setting combination of bit 4 of the flash memory control register 2 and this bit as shown in table 12, e/w is dis- abled to user block in the cpu rewriting mode. bit 3 of the flash memory control register 0 is the flash memory re- set bit used to reset the control circuit of internal flash memory. this bit is used when flash memory access has failed. when the cpu rewrite mode select bit is 1 , setting 1 for this bit resets the control circuit. to release the reset, it is necessary to set this bit to 0 . bit 5 of the flash memory control register 0 is the user rom area select bit and is valid only in the boot mode. setting this bit to 1 in the boot mode switches an accessible area from the boot rom area to the user rom area. to use the cpu rewrite mode in the boot mode, set this bit to 1 . to rewrite bit 5, execute the user- original reprogramming control software transferred to the internal ram in advance. bit 6 of the flash memory control register 0 is the program status flag. this bit is set to 1 when writing to flash memory is failed. when program error occurs, the block cannot be used. bit 7 of the flash memory control register 0 is the erase status flag. this bit is set to 1 when erasing flash memory is failed. when erase error occurs, the block cannot be used. figure 66 shows the flash memory control register 1. bit 0 of the flash memory control register 1 is the erase suspend enable bit. by setting this bit to 1 , the erase suspend mode to suspend erase processing temporaly when block erase command is executed can be used. in order to set this bit to 1 , writing 0 and 1 in succession to bit 0. in order to set this bit to 0 , write 0 only to bit 0. bit 1 of the flash memory control register 1 is the erase suspend request bit. by setting this bit to 1 when erase suspend enable bit is 1 , the erase processing is suspended. fig. 65 structure of flash memory control register 0 fig. 66 structure of flash memory control register 1 b7 b0 flash memory control register 0 (fmcr0: address : 0fe0 16 : initial value: 01 16 ) ry/by status flag 0 : busy (being written or erased) 1 : ready cpu rewrite mode select bit (note 1) 0 : cpu rewrite mode invalid 1 : cpu rewrite mode valid 8kb user block e/w enable bit (notes 1, 2) 0 : e/w disabled 1 : e/w enabled flash memory reset bit (notes 3, 4) 0 : normal operation 1 : reset not used (do not write 1 to this bit.) user rom area select bit (note 5) 0 : boot rom area is accessed 1 : user rom area is accessed program status flag 0: pass 1: error erase status flag 0: pass 1: error notes 1: for this bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. for this bit to be set to 0 , write 0 only to this bit. 2: this bit can be written only when cpu rewrite mode select bit is 1 . 3: effective only when the cpu rewrite mode select bit = 1 . fix this bit to 0 when the cpu rewrite mode select bit is 0 . 4: when setting this bit to 1 (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 s. 5: write to this bit in program on ram notes 1: for this bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. for this bit to be set to 0 , write 0 only to this bit. 2: effective only when the suspend enable bit = 1 . b7 b0 erase suspend enble bit (n otes 1) 0 : suspend invalid 1 : suspend valid erase suspend request bit (notes 2) 0 : erase restart 1 : suspend request erase suspend flag 0 : erase active 1 : erase inactive (erase suspend mode) not used (do not write 1 to this bit.) not used (do not write 1 to this bit.) flash memory control register 1 (fmcr1: address : 0fe1 16 : initial value: 40 16 ) bit 6 of the flash memory control register 1 is the erase suspend flag. this bit is cleared to 0 at the flash erasing.
rev.3.02 nov 05, 2004 page 71 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 68 cpu rewrite mode set/release flowchart figure 68 shows a flowchart for setting/releasing cpu rewrite mode. fig. 67 structure of flash memory control register 2 table 12 state of e/w inhibition function all user block e/w enable bit 0 0 1 1 8 kb user block e/w enable bit 0 1 0 1 8 kb ? 2 block addresses c000 16 to ffff 16 e/w disabled e/w disabled e/w disabled e/w enabled 16 kb + 24 kb block addresses 2000 16 to bfff 16 e/w disabled e/w disabled e/w enabled e/w enabled data block addresses 1000 16 to 1fff 16 e/w enabled e/w enabled e/w enabled e/w enabled notes 1: for this bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. for this bit to be set to 0 , write 0 only to this bit. 2: effective only when the cpu rewrite mode select bit = 1 . b7 b0 not used not used (do not write 1 to this bit.) all user block e/w enable bit (notes 1, 2) 0 : e/w disabled 1 : e/w enabled flash memory control register 2 (fmcr2: address : 0fe2 16 : initial value: 45 16 ) not used not used e n d s t a r t e x e c u t e r e a d a r r a y c o m m a n d ( n o t e 2 ) single-chip mode or boot mode set cpu mode register (note 1) using software command executes erase, program, or other operation j u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d t o i n t e r n a l r a m ( s u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s r a m ) transfer cpu rewrite mode control program to internal ram n o t e s1 : s e t t h e m a i n c l o c k a s f o l l o w s d e p e n d i n g o n t h e c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s o f c p u m o d e r e g i s t e r ( b i t s 6 , 7 o f a d d r e s s 0 0 3 b 1 6 ) . 2 : b e f o r e e x i t i n g t h e c p u r e w r i t e m o d e a f t e r c o m p l e t i n g e r a s e o r p r o g r a m o p e r a t i o n , a l w a y s b e s u r e t o e x e c u t e t h e r e a d a r r a y c o m m a n d . w r i t e 0 t o c p u r e w r i t e m o d e s e l e c t b i t s e t c p u r e w r i t e m o d e s e l e c t b i t t o 1 ( b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) s e t a l l u s e r b l o c k e / w e n a b l e b i t t o 1 ( b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) s e t 8 k b u s e r b l o c k e / w e n a b l e b i t ( a t e / w d i s a b l e d ; w r i t i n g 0 , a t e / w e n a b l e d ; w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) s e t a l l u s e r b l o c k e / w e n a b l e b i t t o 0 s e t 8 k b u s e r b l o c k e / w e n a b l e b i t t o 0
rev.3.02 nov 05, 2004 page 72 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. take the notes described below when rewriting the flash memory in cpu rewrite mode. during cpu rewrite mode, set the system clock to 4.0 mhz or less using the clock division ratio selection bits (bits 6 and 7 of ad- dress 003b 16 ). the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode. the interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. if the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. reset is always valid. the mcu is activated using the boot mode at release of reset in the condition of cnvss = h , so that the pro- gram will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area.
rev.3.02 nov 05, 2004 page 73 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 13 lists the software commands. after setting the cpu rewrite mode select bit to 1 , execute a soft- ware command to specify an erase or program operation. each software command is explained below. read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (d 0 to d 7 ). the read array mode is retained until another command is written. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr4 and sr5 of the status register after they have been set. these bits indicate that opera- tion has ended in an error. to use this command, write the command code 50 16 in the first bus cycle. program command (40 16 ) program operation starts when the command code 40 16 is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. whether the write operation is completed can be confirmed by _____ read status register or the ry/by status flag. when the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status register mode re- mains active until the read array command (ff 16 ) is written. table 13 list of software commands (cpu rewrite mode) the ry/by status flag of the flash memory control register is 0 during write operation and 1 when the write operation is com- pleted as is the status register bit 7. at program end, program results can be checked by reading the status register. fig. 69 program flowchart c o m m a n d p r o g r a m clear status register r e a d a r r a y r e a d s t a t u s r e g i s t e r x x first bus cycle second bus cycle ff 16 70 16 50 16 40 16 write write write write xs r d r e a d write (note 1) wa ( n o t e 2 ) w d ( n o t e 2 ) b l o c k e r a s e20 16 write d 0 1 6 write b a ( n o t e 3 ) mode a d d r e s s mode a d d r e s s d a t a ( d 0 t o d 7 ) (d 0 to d 7 ) ( n o t e 4 ) n o t e s 1 : s r d = s t a t u s r e g i s t e r d a t a 2 : w a = w r i t e a d d r e s s , w d = w r i t e d a t a 3 : b a = b l o c k a d d r e s s t o b e e r a s e d ( i n p u t t h e m a x i m u m a d d r e s s o f e a c h b l o c k . ) 4 : x d e n o t e s a g i v e n a d d r e s s i n t h e u s e r r o m a r e a . cycle number 1 2 1 2 2 x x x d a t a start w r i t e 4 0 1 6 r e a d s t a t u s r e g i s t e r p r o g r a m c o m p l e t e d n o y e s w r i t e a d d r e s s w r i t e d a t a sr4 = 0 ? p r o g r a m e r r o r n o yes s r 7 = 1 ? o r r y / b y = 1 ? w r i t e
rev.3.02 nov 05, 2004 page 74 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed by read status register or the ry/by status flag of flash memory control register. at the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains ac- tive until the read array command (ff 16 ) is written. the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg- ister bit 7. after the block erase ends, erase results can be checked by read- ing the status register. for details, refer to the section where the status register is detailed. fig. 70 erase flowchart write 20 16 d0 16 block address erase completed (write read command ff 16 ) no yes start write sr5 = 0 ? erase error yes no sr7 = 1 ? or ry/by = 1 ? read status register
rev.3.02 nov 05, 2004 page 75 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 14 definition of each bit in status register the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to 80 16 . table 14 shows the status register. each bit in this register is ex- plained below. sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to 0 (busy) during write or erase operation and is set to 1 when these operations ends. after power-on, the sequencer status is set to 1 (ready). erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is reset to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to 1 . the program status is reset to 0 when it is cleared. if 1 is written for any of the sr5 and sr4 bits, the read array, program, and block erase commands are not accepted. before ex- ecuting these commands, execute the clear status register command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to 1 . each bit of srd bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) sequencer status reserved erase status program status reserved reserved reserved reserved status name 1 ready - terminated in error terminated in error - - - - 0 busy - terminated normally terminated normally - - - - definition
rev.3.02 nov 05, 2004 page 76 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 71 shows a full status check flowchart and the action to be taken when each error occurs. fig. 71 full status check flowchart and remedial procedure for errors r e a d s t a t u s r e g i s t e r sr4 = 1 and sr5 = 1 ? n o y e s s r 5 = 0 ? y e s er a s e e r r o r n o sr4 = 0 ? y e s no command sequence error p r o g r a m e r r o r e n d ( b l o c k e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. n o t e : w h e n o n e o f s r 5 a n d s r 4 i s s e t t o 1 , n o n e o f t h e r e a d a r r a y , p r o g r a m , a n d b l o c k e r a s e c o m m a n d s i s a c c e p t e d . e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( 5 0 1 6 ) b e f o r e e x e c u t i n g t h e s e c o m m a n d s . should a program error occur, the block in error cannot be used.
rev.3.02 nov 05, 2004 page 77 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check func- tion for use in standard serial i/o mode. (1) rom code protect function the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control address (address ffdb 16 ) in paral- lel i/o mode. figure 72 shows the rom code protect control address (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of rom code protect bits is set to 0 , the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , the rom code protect is turned off, so that the contents of internal flash memory can be readout or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code protect reset bits. rewriting of only the rom code protect control address (address ffdb 16 ) cannot be performed. when rewriting the rom code pro- tect reset bit, rewrite the whole user rom area (block 0) containing the rom code protect control address. fig. 72 structure of rom code protect control address rom code protect control address (address ffdb 16 ) romcp (ff 16 when shipped) r e s e r v e d b i t s ( 1 a t r e a d / w r i t e ) r o m c o d e p r o t e c t l e v e l 2 s e t b i t s ( r o m c p 2 ) ( n o t e s 1 , 2 ) b 3 b 2 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d r o m c o d e p r o t e c t r e s e t b i t s ( r o m c r ) ( n o t e 3 ) b 5 b 4 0 0 : p r o t e c t r e m o v e d 0 1 : p r o t e c t s e t b i t s e f f e c t i v e 1 0 : p r o t e c t s e t b i t s e f f e c t i v e 1 1 : p r o t e c t s e t b i t s e f f e c t i v e r o m c o d e p r o t e c t l e v e l 1 s e t b i t s ( r o m c p 1 ) ( n o t e 1 ) b 7 b 6 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d b 0 b 7 notes 1 : when rom code protect is turned on, the internal flash memory is protected against readout or modification in parallel i/o mode. 2 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 3 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in serial i/o mode or cpu rewrite mode. 11
rev.3.02 nov 05, 2004 page 78 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. (2) id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the pro- grammer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a pro- gram which has had the id code preset at these addresses to the flash memory. fig. 73 id code store addresses rom code protect control id7 id6 id5 id4 id3 id2 id1 ffdb 16 ffda 16 ffd9 16 ffd8 16 ffd7 16 ffd6 16 ffd5 16 ffd4 16 address interrupt vector area
rev.3.02 nov 05, 2004 page 79 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. the parallel i/o mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. use the external device (writer) only for 3803 group (spec. h) flash memory version. for details, refer to the user s manual of each writer manufacturer. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 64 can be rewritten. both areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size and located at addresses f000 16 through ffff 16 . make sure program and block erase op- erations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the fac-tory. therefore, using the mcu in standard serial i/o mode, do not rewrite to the boot rom area.
rev.3.02 nov 05, 2004 page 80 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this mode requires a purpose-specific pe- ripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu rewrite mode), rewrite data input and so forth. the standard serial i/o mode is started by connecting ??to the cnvss pin and ??to the p4 5 (bootent) pin, and releasing the reset operation. (in the ordinary microcomputer mode, set cnvss pin to ??level.) this control program is written in the boot rom area when the product is shipped from renesas. accordingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. the standard serial i/ o mode has standard serial i/o mode 1 of the clock synchronous serial and standard serial i/o mode 2 of the clock asynchronous serial. tables 15 and 16 show description of pin function (standard serial i/o mode). figures 74 to 77 show the pin connections for the standard serial i/o mode. in standard serial i/o mode, only the user rom area shown in figure 64 can be rewritten. the boot rom area cannot be written. in standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, this function determines whether the id code sent from the peripheral unit (programmer) and those writ- ten in the flash memory match. the commands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
rev.3.02 nov 05, 2004 page 81 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. pin name signal name i/o v cc ,v ss power supply i cnv ss cnv ss i reset reset input i x in clock input i x out clock output o av ss analog power supply input v ref reference voltage input i p0 0 p0 7 ,p1 0 p1 7 , i/o port i/o p2 0 p2 7 ,p3 0 p3 7 , p4 0 p4 3 ,p5 0 p5 7 , p6 0 p6 7 p4 4 rxd input i p4 5 txd output o p4 6 s clk input i p4 7 busy output o table 15 description of pin function (flash memory serial i/o mode 1) function apply 2.7 to 5.5 v to the vcc pin and 0 v to the vss pin. after input of port is set, input h level. reset input pin. to reset the microcomputer, reset pin should be held at an l level for 16 cycles or more of x in . connect an oscillation circuit between the x in and x out pins. as for the connection method, refer to the clock generating circuit . connect avss to vss. apply reference voltage of a-d to this pin. input l or h level, or keep open. serial data input pin. serial data output pin. serial clock input pin. busy signal output pin. pin name signal name i/o v cc ,v ss power supply i cnv ss cnv ss i reset reset input i x in clock input i x out clock output o avss analog power supply input v ref reference voltage input i p0 0 p0 7 ,p1 0 p1 7 , i/o port i/o p2 0 p2 7 ,p3 0 p3 7 , p4 0 p4 3 ,p5 0 p5 7 , p6 0 p6 7 p4 4 rxd input i p4 5 txd output o p4 6 s clk input i p4 7 busy output o table 16 description of pin function (flash memory serial i/o mode 2) function apply 2.7 to 5.5 v to the vcc pin and 0 v to the vss pin. after input of port is set, input h level. reset input pin. to reset the microcomputer, reset pin should be held at an l level for 16 cycles or more of x in . connect an oscillation circuit between the x in and x out pins. as for the connection method, refer to the clock generating circuit . connect avss to vss. apply reference voltage of a-d to this pin. input l or h level, or keep open. serial data input pin. serial data output pin. input l level. busy signal output pin.
rev.3.02 nov 05, 2004 page 82 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 74 connection for standard serial i/o mode 1 (M38039ffhfp/hp/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 p3 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 M38039ffhfp/hp/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 v ss reset cnvss ? v cc rxd txd sclk busy ? connect oscillation circuit. indicates flash memory pin. packa g e t yp e: 64p6n-a/64p6q-a/64p6u-a
rev.3.02 nov 05, 2004 page 83 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 75 connection for standard serial i/o mode 2 (M38039ffhfp/hp/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 p3 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 M38039ffhfp/hp/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 v ss cnvss ? v cc rxd txd l input busy reset ? connect oscillation circuit. packa g e t yp e: 64p6n-a/64p6q-a/64p6u-a indicates flash memory pin.
rev.3.02 nov 05, 2004 page 84 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 76 connection for standard serial i/o mode 1 (M38039ffhsp) v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 p3 3 p3 6 / s clk3 p3 7 / s rdy3 p4 7 /s rdy1 / cntr 2 M38039ffhsp 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 64 ? v ss reset cnv ss r x d t x d s clk busy v cc ? connect oscillation circuit. package type: 64p4b indicates flash memor y p in.
rev.3.02 nov 05, 2004 page 85 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 77 connection for standard serial i/o mode 2 (M38039ffhsp) v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 p3 3 p3 6 / s clk3 p3 7 / s rdy3 p4 7 /s rdy1 / cntr 2 M38039ffhsp 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 64 ? v ss cnv ss r x d t x d l input busy v cc reset ? connect oscillation circuit. package type: 64p4b indicates flash memor y p in.
rev.3.02 nov 05, 2004 page 86 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 78 operating waveform for standard serial i/o mode 1 fig. 79 operating waveform for standard serial i/o mode 2 power source reset cnv ss p4 5 (t x d) p4 6 (s clk ) p4 7 (busy) p4 4 (r x d) td(cnv ss -reset) td(p4 5 -reset) symbol td(cnvss-reset) td(p4 5 -reset) limits min. typ. max. unit 0 0 ms ms notes: in the standard serial i/o mode 1, input h to the p4 6 pin. be sure to set the cnvss pin to h before rising reset. be sure to set the p4 5 pin to h before rising reset. power source reset cnv ss p4 5 (t x d) p4 7 (busy) p4 4 (r x d) p4 6 (s clk ) td(cnv ss -reset) td(p4 5 -reset) symbol td(cnvss-reset) td(p4 5 -reset) limits min. typ. max. unit 0 0 ms ms notes: in the standard serial i/o mode 2, input h to the p4 6 pin. be sure to set the cnvss pin to h before rising reset. be sure to set the p4 5 pin to h before rising reset.
rev.3.02 nov 05, 2004 page 87 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the instruction with the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transfer is completed. when in serial i/os 1 and 3 (clock-synchronous mode) or in serial i/o2, an external clock is used as synchronous clock, write trans- mission data to the transmit buffer register or serial i/o2 register, during transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp instruction during an a-d conversion. d-a converter the accuracy of the d-a converter becomes rapidly poor under the v cc = 4.0 v or less condition; a supply voltage of v cc 4.0 v is recommended. when a d-a converter is not used, set all values of d-ai conversion registers (i=1, 2) to 00 16 . instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock is double of the x in period in high-speed mode.
rev.3.02 nov 05, 2004 page 88 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f 0.1 f is recom- mended. power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. flash memory version the cnvss pin determines the flash memory mode. to improve the noise reduction, connect a track between cnvss pin and vss pin or vcc pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational interference even if it is connected to vss pin or vcc pin via a resistor. electric characteristic differences between mask rom and flash memory version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufac- turing processes, built-in rom, and layout pattern etc.when manufacturing an application system with the flash memory ver- sion and then switching to use of the mask rom version, please conduct evaluations equivalent to the system evaluations con- ducted for the flash memory version. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom confirmation form ? 2.mark specification form ? 3.data to be written to rom, in eprom form (three identical cop- ies) ? for the mask rom confirmation and the mark specifications, refer to the renesas technology corp. homepage (http://www.renesas.com/en/rom).
rev.3.02 nov 05, 2004 page 89 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics absolute maximum ratings table 17 absolute maximum ratings power source voltages input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , v ref input voltage p3 2 , p3 3 input voltage ____________ reset, x in input voltage cnv ss output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 , x out output voltage p3 2 , p3 3 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings 0.3 to 6.5 0.3 to v cc +0.3 0.3 to 5.8 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to 5.8 1000 (note) 20 to 85 65 to 125 v v v v v v v mw c c unit note: this value is 300 mw except sp package. all voltages are based on vss. output transistors are cut off. ta = 25 c
rev.3.02 nov 05, 2004 page 90 of 108 3803 group (spec. h) mask rom version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 18 recommended operating conditions (1) (mask rom version) (v cc = 1.8 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) recommended operating conditions 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc 5.5 5.5 v cc v cc 0.16v cc 0.2v cc 0.16v cc 0.2v cc 0.16v cc power source voltage h input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 h input voltage p3 2 , p3 3 h input voltage ____________ reset, x in , x cin , cnv ss l input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 l input voltage ____________ reset, cnv ss l input voltage x in , x cin symbol parameter limits min. v v v v v v v v v v v v v v v v v v v v v v unit 2.2 2.0 2.2 2.7 4.0 4.5 1.8 2.2 2.7 4.5 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 typ. max. f(x in ) 2.1 mhz f(x in ) 4.2 mhz f(x in ) 8.4 mhz f(x in ) 12.5 mhz f(x in ) 16.8 mhz f(x in ) 6.3 mhz f(x in ) 8.4 mhz f(x in ) 12.5 mhz f(x in ) 16.8 mhz power source voltage (note 1) v cc v ss v ih v ih v il v il v il v ih when start oscillating (note 2) high-speed mode f( ) = f(x in )/2 middle-speed mode f( ) = f(x in )/8 1.8 v cc < 2.7 v 2.7 v cc 5.5 v 1.8 v cc < 2.7 v 2.7 v cc 5.5 v 1.8 v cc < 2.7 v 2.7 v cc 5.5 v 1.8 v cc < 2.7 v 2.7 v cc 5.5 v 1.8 v cc < 2.7 v 2.7 v cc 5.5 v 1.8 v cc 5.5 v 0.85v cc 0.8v cc 0.85v cc 0.8v cc 0.85v cc 0.8v cc 0 0 0 0 0 notes 1: when using a-d converter, see a-d converter recommended operating conditions. 2: the start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and ope rating temperature range, etc.. particularly a high-frequency oscillator might require some notes in the low voltage operation. conditions
rev.3.02 nov 05, 2004 page 91 of 108 3803 group (spec. h) flash memory version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 19 recommended operating conditions (2) (flash memory version) (v cc = 2.7 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 v cc 5.5 v cc v cc 0.2v cc 0.2v cc 0.16v cc 0.4 power source voltage h input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 h input voltage p3 2 , p3 3 h input voltage ____________ reset, x in , cnv ss h input voltage x cin l input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 ,p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 l input voltage ____________ reset, cnv ss l input voltage x in l input voltage x cin symbol parameter limits min. v v v v v v v v v v v v v v v unit 2.7 2.7 4.0 4.5 2.7 4.5 5.0 5.0 5.0 5.0 5.0 5.0 0 typ. max. f(x in ) 8.4 mhz f(x in ) 12.5 mhz f(x in ) 16.8 mhz f(x in ) 12.5 mhz f(x in ) 16.8 mhz power source voltage (note 1) v cc v ss v ih v ih v il v il v il v ih when start oscillating (note 2) high-speed mode f( ) = f(x in )/2 middle-speed mode f( ) = f(x in )/8 0.8v cc 0.8v cc 0.8v cc 2 0 0 notes 1: when using a-d converter, see a-d converter recommended operating conditions. 2: the start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and ope rating temperature range, etc.. particularly a high-frequency oscillator might require some notes in the low voltage operation. conditions v ih v il
rev.3.02 nov 05, 2004 page 92 of 108 3803 group (spec. h) mask rom version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 20 recommended operating conditions (3) (mask rom version) (v cc = 1.8 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) main clock input oscillation frequency (note 1) f(x cin ) symbol parameter limits min. mhz mhz mhz mhz mhz mhz mhz mhz mhz khz unit typ. max. notes 1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 32.768 f(x in ) sub-clock input oscillation frequency (notes 1, 2) conditions high-speed mode f( ) = f(x in )/2 middle-speed mode f( ) = f(x in )/8 2.0 v cc < 2.2 v 2.2 v cc < 2.7 v 2.7 v cc < 4.0 v 4.0 v cc < 4.5 v 4.5 v cc 5.5 v 1.8 v cc < 2.2 v 2.2 v cc < 2.7 v 2.7 v cc < 4.5 v 4.5 v cc 5.5 v (20 ? v cc -36) ? 1.05 2 (24 ? v cc -40.8) ? 1.05 3 (9 ? v cc -0.3) ? 1.05 3 (24 ? v cc -60) ? 1.05 3 16.8 (15 ? v cc -9) ? 1.05 3 (24 ? v cc -28.8) ? 1.05 3 (15 ? v cc +39) ? 1.1 7 16.8 50
rev.3.02 nov 05, 2004 page 93 of 108 3803 group (spec. h) flash memory version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 21 recommended operating conditions (4) (flash memory version) (v cc = 2.7 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) main clock input oscillation frequency (note 1) f(x cin ) symbol parameter limits min. mhz mhz mhz mhz mhz khz unit typ. max. notes 1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 32.768 f(x in ) sub-clock input oscillation frequency (notes 1, 2) conditions high-speed mode f( ) = f(x in )/2 middle-speed mode f( ) = f(x in )/8 2.7 v cc < 4.0 v 4.0 v cc < 4.5 v 4.5 v cc 5.5 v 2.7 v cc < 4.5 v 4.5 v cc 5.5 v (9 ? v cc -0.3) ? 1.05 3 (24 ? v cc -60) ? 1.05 3 16.8 (15 ? v cc +39) ? 1.1 7 16.8 50
rev.3.02 nov 05, 2004 page 94 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 22 recommended operating conditions (5) (mask rom version: v cc = 1.8 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) 80 80 80 80 80 40 40 40 40 40 10 10 20 5 5 10 h total peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 (note 1) h total peak output current p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 1) l total peak output current p0 0 p0 7 , p1 0 p1 7 , p3 0 p3 7 (note 1) l total peak output current p2 0 p2 7 (note 1) l total peak output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 (note 1) h total average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 (note 1) h total average output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 (note 1) l total average output current p0 0 p0 7 , p1 0 p1 7 , p3 0 p3 7 (note 1) l total average output current p2 0 p2 7 (note 1) l total average output current p4 0 p4 7 ,p5 0 p5 7 , p6 0 p6 7 (note 1) h peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 2) l peak output current p0 0 p0 7 , p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 2) l peak output current p2 0 p2 7 (note 2) h average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1, p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 3) l average output current p0 0 p0 7 , p1 0 p1 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 3) l average output current p2 0 p2 7 (note 3) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma unit typ. max. notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms.
rev.3.02 nov 05, 2004 page 95 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 23 electrical characteristics (1) (mask rom version: v cc = 1.8 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = 20 to 85 c, unless otherwise noted) electrical characteristics h output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 (note 1) l output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 l output voltage p2 0 p2 7 hysteresis cntr 0 , cntr 1 , cntr 2 , int 0 int 4 hysteresis rxd1, s clk1 , s in2 , s clk2 , rxd 3 , s clk3 ____________ hysteresis reset h input current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 h input current ____________ reset, cnv ss h input current x in l input current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 l input current ____________ reset,cnv ss l input current x in l input current (at pull-up) p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 , p3 1 , p3 4 p3 7 , p4 0 p4 7 , p5 0 p5 7 , p6 0 p6 7 ram hold voltage limits v v v v v v v v v a a a a a a a a v parameter min. typ. max. symbol unit note 1: p3 5 is measured when the p3 5 /txd 3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is 0 . p4 5 is measured when the p4 5 /txd 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is 0 . i oh = 10 ma v cc = 4.0 to 5.5 v i oh = 1.0 ma v cc = 1.8 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v i ol = 1.6 ma v cc = 1.8 to 5.5 v i ol = 20 ma v cc = 4.0 to 5.5 v i ol = 1.6 ma v cc = 1.8 to 5.5 v v i = v cc (pin floating. pull-up transistors off ) v i = v cc v i = v cc v i = v ss (pin floating. pull-up transistors off ) v i = v ss v i = v ss v i = v ss v cc = 5.0 v v i = v ss v cc = 3.0 v when clock stopped v cc 2.0 v cc 1.0 80 30 1.8 test conditions 0.4 0.5 0.5 4.0 4.0 210 70 2.0 1.0 2.0 0.4 5.0 5.0 5.0 5.0 420 140 v cc v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il v ram
rev.3.02 nov 05, 2004 page 96 of 108 3803 group (spec. h) mask rom version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 24 electrical characteristics (2) (mask rom version) (v cc = 1.8 to 5.5 v, t a = 20 to 85 c, f(x cin )=32.768kh z (stoped in middle-speed mode), output transistors off , ad converter not operated) power source current limits parameter max. symbol unit f(x in ) = 16.8 mhz f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 4.2 mhz f(x in ) = 16.8 mhz (in wit state) f(x in ) = 8.4 mhz f(x in ) = 4.2 mhz f(x in ) = 2.1 mhz f(x in ) = 16.8 mhz f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 16.8 mhz (in wit state) f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 6.3 mhz f(x in ) = stopped in wit state f(x in ) = stopped in wit state f(x in ) = stopped in wit state ta = 25 c ta = 85 c f(x in ) = 16.8 mhz, v cc = 5v in middle-, high-speed mode test conditions 15.0 12.0 9.0 5.0 3.6 3.8 2.0 1.2 7.0 6.0 5.0 3.3 3.0 2.4 2.0 200 70 40 15 15 6 1.0 10 i cc ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a a a a a a a a high-speed mode middle-speed mode low-speed mode in stp state (all oscillation stopped) increment when a-d conversion is executed typ. min. 8.0 6.5 5.0 2.5 2.0 1.9 1.0 0.6 4.0 3.0 2.5 1.8 1.5 1.2 1.0 55 40 15 8 6 3 0.1 500 v cc = 5v v cc = 3v v cc = 5v v cc = 3v v cc = 5v v cc = 3v v cc = 2v
rev.3.02 nov 05, 2004 page 97 of 108 3803 group (spec. h) flash memory version preliminary notice: this is not a final specification. some parametric limits are subject to change. table 25 electrical characteristics (3) (flash memory version) (v cc = 2.7 to 5.5 v, t a = 20 to 85 c, f(x cin )=32.768kh z (stoped in middle-speed mode), output transistors off , ad converter not operated) power source current limits parameter max. symbol unit f(x in ) = 16.8 mhz f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 4.2 mhz f(x in ) = 16.8 mhz (in wit state) f(x in ) = 8.4 mhz f(x in ) = 4.2 mhz f(x in ) = 2.1 mhz f(x in ) = 16.8 mhz f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 16.8 mhz (in wit state) f(x in ) = 12.5 mhz f(x in ) = 8.4 mhz f(x in ) = 6.3 mhz f(x in ) = stopped in wit state f(x in ) = stopped in wit state ta = 25 c ta = 85 c f(x in ) = 16.8 mhz, v cc = 5v in middle-, high-speed mode test conditions i cc ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a a a a a a high-speed mode middle-speed mode low-speed mode in stp state (all oscillation stopped) increment when a-d conversion is executed typ. min. 5.5 4.5 3.5 2.2 2.2 2.7 1.8 1.1 3.0 2.4 2.0 2.1 1.7 1.5 1.3 410 4.5 400 3.7 0.55 0.75 1000 v cc = 5v v cc = 3v v cc = 5v v cc = 3v v cc = 5v v cc = 3v 8,3 6.8 5.3 3.3 3.3 4.1 2.7 1.7 4.5 3.6 3.0 3.2 2.6 2.3 2.0 630 6.8 600 5.6 3.0
rev.3.02 nov 05, 2004 page 98 of 108 3803 group (spec. h) mask rom version preliminary notice: this is not a final specification. some parametric limits are subject to change. bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power at a-d converter operated source input current at a-d converter stopped a-d port inout current max. 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) 8-bit a-d mode (note 1) 2.0 v ref < 2.2 v 2.2 v ref 5.5 v 10-bit a-d mode (note 2) 2.2 v ref < 2.7 v 2.7 v ref 5.5 v 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) v ref = 5.0 v v ref = 5.0 v table 27 a-d converter characteristics (mask rom version) (v cc = 2.0 to 5.5 v, v ss = av ss = 0 v, t a = 20 to 85 c, unless otherwise noted) unit limits parameter t conv r ladder i vref i i(ad) test conditions symbol a-d converter characteristics symbol parameter limits min. unit typ. max. conditions table 26 a-d converter recommended operating conditions (mask rom version) (v cc = 2.0 to 5.5 v, v ss = av ss = 0 v,t a = 20 to 85 c, unless otherwise noted) power source voltage (when a-d converter is used) analog reference voltage analog power source voltage analog input voltage main clock oscillation frequency (when a-d converter is used) v cc v ref av ss v ia f(x in ) v v v v mh z 2.0 2.2 2.0 0 0.5 0.5 0.5 0.5 0.5 5.0 5.0 0 2.0 v cc < 2.2 v 2.2 v cc < 2.7 v 2.7 v cc < 4.0 v 4.0 v cc < 4.5 v 4.5 v cc 5.5 v 5.5 5.5 v cc v cc (20 ? v cc -36) ? 1.05 2 (24 ? v cc -40.8) ? 1.05 3 (9 ? v cc -0.3) ? 1.05 3 (24 ? v cc -60) ? 1.05 3 16.8 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) notes 1: 8-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 1 . 2: 10-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 0 . notes 1: 8-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 1 . 2: 10-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 0 . note 1: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 . table 28 d-a converter characteristics (mask rom version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = 20 to 85 c, unless otherwise noted) bit % % s k ? ma resolution absolute accuracy 4.0 v ref 5.5 v 2.7 v ref < 4.0 v setting time output resistor reference power source input current (note 1) min. unit limits parameter tsu ro i vref test conditions symbol d-a converter characteristics 8 10 3 2 5 4 50 61 100 200 5 5 12 50 35 150 min. typ. typ. max. 2 3.5 8 1.0 2.5 3 5 3.2
rev.3.02 nov 05, 2004 page 99 of 108 3803 group (spec. h) flash memory version preliminary notice: this is not a final specification. some parametric limits are subject to change. bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power at a-d converter operated source input current at a-d converter stopped a-d port inout current max. 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) 8-bit a-d mode (note 1) 2.7 v ref 5.5 v 10-bit a-d mode (note 2) 2.7 v ref 5.5 v 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) v ref = 5.0 v v ref = 5.0 v table 30 a-d converter characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = 20 to 85 c, unless otherwise noted) unit limits parameter t conv r ladder i vref i i(ad) test conditions symbol symbol parameter limits min. unit typ. max. conditions table 29 a-d converter recommended operating conditions (flash memory version) (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v,t a = 20 to 85 c, unless otherwise noted) power source voltage (when a-d converter is used) analog reference voltage analog power source voltage analog input voltage main clock oscillation frequency (when a-d converter is used) v cc v ref av ss v ia f(x in ) v v v v mh z 2.7 2.7 2.0 0 0.5 0.5 0.5 5.0 5.0 0 2.7 v cc < 4.0 v 4.0 v cc < 4.5 v 4.5 v cc 5.5 v 5.5 5.5 v cc v cc (9 ? v cc -0.3) ? 1.05 3 (24 ? v cc -60) ? 1.05 3 16.8 8-bit a-d mode (note 1) 10-bit a-d mode (note 2) note 1: 8-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 1 . 2: 10-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 0 . note 1: 8-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 1 . 2: 10-bit a-d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is 0 . note 1: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 . table 31 d-a converter characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = 20 to 85 c, unless otherwise noted) bit % % s k ? ma resolution absolute accuracy 4.0 v ref 5.5 v 2.7 v ref < 4.0 v setting time output resistor reference power source input current (note 1) min. unit limits parameter tsu ro i vref test conditions symbol d-a converter characteristics 8 10 2 4 50 61 100 200 5 5 12 50 35 150 min. typ. typ. max. 2 3.5 8 1.0 2.5 3 5 3.2 table 32 power source circuit timing characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = 20 to 85 c, unless otherwise noted) ms internal power source stable time at power-on min. unit limits parameter td(p r) test conditions symbol power source circuit timing characteristics typ. max. 2 2.7 v cc < 5.5 v
rev.3.02 nov 05, 2004 page 100 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. table 33 timing requirements (1) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) timing requirements and switching characteristics t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) limits x in cycle ns ns ns s s s ns ns ns ns ns parameter max. symbol unit typ. reset input ??pulse width (mask rom version) reset input ??pulse width (flash memory version) main clock x in input cycle time main clock x in input ??pulse width main clock x in input ??pulse width sub-clock x cin input cycle time sub-clock x cin input ??pulse width sub-clock x cin input ??pulse width cntr 0 ?ntr 2 input cycle time cntr 0 ?ntr 2 input ??pulse width cntr 0 ?ntr 2 input ??pulse width int 00 , int 01 , int 1, int 2, int 3, int 40 , int 41 input ??pulse width int 00 , int 01 , int 1, int 2, int 3, int 40 , int 41 input ??pulse width min. 16 td(p-r) ms + 16 59.5 10000/(86v cc -219) 26 ? 10 3 /(82v cc -3) 10000/(84v cc -143) 10000/(105v cc -189) 25 4000/(86v cc -219) 10000/(82v cc -3) 4000/(84v cc -143) 4000/(105v cc -189) 25 4000/(86v cc -219) 10000/(82v cc -3) 4000/(84v cc -143) 4000/(105v cc -189) 20 5 5 120 160 250 500 1000 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v
rev.3.02 nov 05, 2004 page 101 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. note : when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ??(clock synchronous). divide this value by four when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ??(uart). table 34 timing requirements (2) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) limits ns ns ns ns ns ns ns ns ns ns parameter max. symbol unit typ. min. 250 320 500 1000 2000 120 150 240 480 950 120 150 240 480 950 70 90 100 200 400 32 40 50 100 200 500 650 1000 2000 4000 200 260 400 950 2000 200 260 400 950 2000 100 130 200 400 800 100 130 150 300 600 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v serial i/o1, serial i/o3 clock input cycle time (note) serial i/o1, serial i/o3 clock input ??pulse width (note) serial i/o1, serial i/o3 clock input ??pulse width (note) serial i/o1, serial i/o3 clock input setup time serial i/o1, serial i/o3 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 clock input setup time serial i/o2 clock input hold time t c (s clk1 ), t c (s clk3 ) t wh (s clk1 ), t wh (s clk3 ) t wl (s clk1 ), t wl (s clk3 ) t su (r x d 1 -s clk1 ), t su (r x d 3 -s clk3 ) t h (s clk1 -r x d 1 ), t h (s clk3 -r x d 3 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 )
rev.3.02 nov 05, 2004 page 102 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. note: when the p4 5 /txd 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?? table 35 switching characteristics (1) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) limits ns ns ns ns ns ns ns ns ns ns parameter max. 140 200 350 400 420 30 35 40 45 50 30 35 40 45 50 200 250 300 350 400 symbol unit typ. 0 0 0 0 0 min. tc(s clk1 )2-30, tc(s clk3 )/2-30 tc(s clk1 )2-35, tc(s clk3 )/2-35 tc(s clk1 )2-40, tc(s clk3 )/2-40 tc(s clk1 )2-45, tc(s clk3 )/2-45 tc(s clk1 )2-50, tc(s clk3 )/2-50 tc(s clk1 )2-30, tc(s clk3 )/2-30 tc(s clk1 )2-35, tc(s clk3 )/2-35 tc(s clk1 )2-40, tc(s clk3 )/2-40 tc(s clk1 )2-45, tc(s clk3 )/2-45 tc(s clk1 )2-50, tc(s clk3 )/2-50 -30 -30 -30 -30 -30 tc(s clk2 )/2-160 tc(s clk2 )/2-200 tc(s clk2 )/2-240 tc(s clk2 )/2-260 tc(s clk2 )/2-280 tc(s clk2 )/2-160 tc(s clk2 )/2-200 tc(s clk2 )/2-240 tc(s clk2 )/2-260 tc(s clk2 )/2-280 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v serial i/o1, serial i/o3 clock output ??pulse width serial i/o1, serial i/o3 clock output ??pulse width serial i/o1, serial i/o3 output delay time (note) serial i/o1, serial i/o3 output valid time (note) serial i/o1, serial i/o3 rise time of clock output serial i/o1, serial i/o3 fall time of clock output serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time t wh (s clk1 ) t wh (s clk3 ) t wl (s clk1 ) t wl (s clk3 ) t d ( s clk1 -t x d 1 ) t d ( s clk3 -t x d 3 ) t v ( s clk1 -t x d 1 ) t v ( s clk3 -t x d 3 ) t r (s clk1 ) t r (s clk3 ) t f (s clk1 ) t f (s clk3 ) t wh (s clk2 ) t wl (s clk2 ) t d ( s clk2 -s out2 ) t v ( s clk2 -s out2 ) test conditions fig. 80
rev.3.02 nov 05, 2004 page 103 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. note: when the p3 5 /txd 3 p4-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is ?? table 36 switching characteristics (2) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, t a = ?0 to 85 ?, unless otherwise noted) limits ns ns ns parameter max. 30 35 40 45 50 30 35 40 45 50 30 35 40 45 50 symbol unit typ. 10 12 15 17 20 10 12 15 17 20 min. 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v 4.5 v cc 5.5 v 4.0 v cc <4.5 v 2.7 v cc <4.0 v 2.2 v cc <2.7 v 2.0 v cc <2.2 v serial i/o2 fall time of clock output cmos rise time of output (note) cmos fall time of output (note) t f (s clk2 ) t r (cmos) t f (cmos) test conditions fig. 80
rev.3.02 nov 05, 2004 page 104 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig.80 circuit for measuring output switching characteristics (1) measurement output pin cmos out p ut 100pf 100pf 1k ? measurement output pin n-channel o p en-drain out p ut fig.81 circuit for measuring output switching characteristics (2)
rev.3.02 nov 05, 2004 page 105 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 82 timing diagram (in single-chip mode) 0 . 2 v c c t w l ( i n t ) 0 . 8 v c c t wh(int) 0.2v cc 0 . 2 v c c 0 . 8 v c c 0.8v cc 0 . 2 v c c t wl(x in ) 0 . 8 v c c t wh(x in) t c ( x i n ) x i n 0 . 2 v c c 0 . 8 v c c t w(reset) r e s e t 0 . 2 v c c t wl(cntr) 0 . 8 v c c t wh(cntr) t c(cntr) t c(s clk1 ), t c(s clk2 ), t c(s clk3 ), t w h ( s c l k 1 ) , t w h ( s c l k 2 ) , t w h ( s c l k 3 ) t h ( s c l k 1 - r x d 1 ) , t h ( s c l k 2 - s i n 2 ) , t h ( s c l k 3 - r x d 3 ) t s u ( r x d 1 - s c l k 1 ) , t s u ( s i n 2 - s c l k 2 ) , t s u ( r x d 3 - s c l k 3 ) t x d 1 t x d 3 s o u t 2 r x d 1 r x d 3 s i n 2 s clk1 s clk2 s clk3 i n t 1 , i n t 2 , i n t 3 i n t 0 0 , i n t 4 0 i n t 0 1 , i n t 4 1 c n t r 0 , c n t r 1 , c n t r 2 0.2v cc t w l ( x c i n ) 0.8v cc t wh(x cin) t c ( x c i n ) x cin t w l ( s c l k 1 ) , t w l ( s c l k 2 ) , t w l ( s c l k 3 ) s i n g l e - c h i p m o d e t i m i n g d i a g r a m t f t r t d ( s c l k 1 -t x d1 ) , t d ( s c l k 2 -s out 2 ) , t d ( s c l k 3 -t x d3 ) t v ( s c l k 1 -t x d1 ) , t v ( s c l k 2 -s out 2 ) , t v ( s c l k 3 -t x d3 )
rev.3.02 nov 05, 2004 page 106 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. 64 33 32 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d sdip64-p-750-1.78 weight(g) 7.9 jedec code eiaj package code lead material alloy 42/cu alloy 64p4b plastic 64pin 750mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.38 3.8 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 1.778 19.05 2.8 0 15 5. 08 e e 1 package outline qfp64-p-1414-0.80 1.11 weight(g) jedec code eiaj package code lead material alloy 42 64p6n-a plastic 64pin 14 ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.5 i 2 1.3 m d 14.6 m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.8 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 64 49 32 48 33 17 16 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f
rev.3.02 nov 05, 2004 page 107 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. lqfp64-p-1010-0.5 weight(g) jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 10mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 10.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 49 48 33 32 17 16 1 64 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e lqfp64-p-1414-0.8 weight(g) jedec code eiaj package code lead material cu alloy 64p6u-a plastic 64pin 14 ? 0.1 0.8 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 i 2 m d 14.4 m e 14.4 0 8 0.1 0.2 1.0 0.7 0.5 0.3 16.2 15.8 14.1 13.9 16.2 15.8 14.0 14.1 13.9 14.0 16.0 16.0 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 0.95 0.6 0.5 0.25 0.75 x a3 recommended mount pad detail f e h e 49 1 16 48 33 64 32 17 h d d a y b x m e f m d l 2 b 2 m e e a 1 a 2 l 1 l lp a3 c
rev.3.02 nov 05, 2004 page 108 of 108 3803 group (spec. h) preliminary notice: this is not a final specification. some parametric limits are subject to change. index mark index mark 64f0g 64pin 6x6mm body flga
revision history rev. date description page summary (1/2) 3803 group (spec.h) data sheet first edition issued ?elete the following :?:kp package is under development. ?able 4 pin description v cc ,v ss apply voltage of 2.7?.5v 1.8v?.5v ?ig.5 memory expansion plan as of dec. 2002 as of mar. 2003 ?otes (address 3a 16 ) (address 003a 16 ), (address 23 16 ) (address 0023 16 ), (address 2a 16 ) (address 002a 16 ), (address 39 16 ) (address 0039 16 ) ?ig.61 system clock generating circuit block diagram ?able 10 recommended operating conditions add : v il ??input voltage x in , x cin 1.8 v cc 5.5v min. 0 ?able 11 recommended operating conditions f(x in ) high-speed mode f( )=f(x in )/2 2.2 v cc 4.0v 2.7 v cc 4.0v ?able 16 a-d converter characteristics v cc 8bit a-d mode, 10bit a-d mode max. 5.0 5.5 ?able 17 d-a converter characteristics v cc = 4.0 to 5.5v 4.0 v cc 5.5v, v cc = 2.7 to 4.0v 2.7 v cc <4.0v ?able 16 a-d converter characteristics, table 17 d-a converter characteristics resolution unit bits bit ?able 18 timing requirements (1) (in high-speed mode) t c (x in ) main clock x in input cycle time 2.7 v cc <4.0 min. 2.6 ? 10 3 /(82v cc -3) 26 ? 10 3 /(82v cc -3) ?able 18 timing requirements (1) (in high-speed mode), table 20 timing requirements (3) (in middle-speed mode) t wh (x cin ) sub-clock input ??pulse width sub-clock x cin input ??pulse width t wl (x cin ) sub-clock input ??pulse width sub-clock x cin input ??pulse width ?able 19 timing requirements (2) (in high-speed mode), table 20 timing requirements (4) (in middle-speed mode) t cl (s clk2 ) t wl (s clk2 ) ?ig.63 timing diagram (in single-chip mode) delete the following underline parts : s clk1 s clk2 s clk3 t f , t r t x d 1 t x d 3 s out2 t d (s clk1 -t x d 1 ), t d (s clk2 -s out2 ), t d (s clk3 -t x d 3 ) t v (s clk1 -t x d 1 ), t v (s clk2 -s out2 ), t v (s clk3 -t x d 3 ) 1,2,6,7 5 7 23 64 68 69 73 75 75,77 76,78 79 stp instruction timing (internal clock) s r q middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) prescaler 12 timer 1 reset or stp instruction (note 2) divider (note 3) ff 16 01 16 stp instruction timing (internal clock) s r q middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) prescaler 12 timer 1 reset or stp instruction (note 2) divider (note 3) reset 1.00 sep. 3, 2001 2.00 may. 28, 2003 3.00 oct. 14, 2003 3.01 jun.25, 2004 flash memory version is added. 6 15 16 table 5 pin description is partly revised. figure 11 memory map of special function register (sfr) is partly revised. table 8 i/o port function is partly revised.
revision history rev. date description page summary (2/2) 3803 group (spec.h) data sheet 3.01 jun.25, 2004 61 61 63 65 69 69 70 70 70 80 86 87 88 97 97 98 98 98 99 101 explanations of ?eset circuit?are partly revised. figure 56 reset circuit example is partly revised. explanations of ?1) stop mode?of ?scillation control?are partly added. figure 56 reset circuit example is partly revied. explanations of ?utline performance?are partly revised. figure 64 structure of flash memory control register 0 is partly revised. figure 66 is partly revised. table 11 is partly revised. figure 67 is partly revised. p4 6 of table 15 is revised. ?otes on programming?is added. ?ata required for mask orders?is added. note of table 16 is partly revised. table 26 a-d converter characteristics (mask rom version) is partly revised. table 27 d-a converter characteristics (mask rom version) is partly revised. table 29 a-d converter characteristics (flash memory version) is partly revised. table 30 d-a converter characteristics (flash memory version) is partly revised. table 31 power source circuit timing characteristics (flash memory version) is added. ____________ tw(reset) of table 32 is revised. table 33 and table 34 of rev.3.00 are eliminated. 3.02 nov.05, 2004 1 1,2,5,8,9 9 35 62 64 65 66 77 80 95 100,101 102,103 104 105 108 memory size rom....16 k to 32 k bytes 16 k to 60 k bytes ram....640 to 1024 bytes 640 to 2048 bytes wg version is added. fig.6 is partly eliminated. (5) pulse width measurement mode is partly revised. fig.58 is partly revised. clock generating circuit is partly revised. fig.60 is partly revised. note 4 of fig.62 is added. functions to inhibit rewriting flash memory version is partly added. standard serial i/o mode is partly revised. outline performance (standard serial i/o mode) is eliminated. table 23 electrical characteristics (1) ? ol ??output voltage p2 0 ?2 7 ?is added. table 33 timing requirements (1), table 34 timing requirements (2) (in high-speed mode) is deleted. mask rom versoin: vcc = 1.8 to 5.5v vcc = 2.0 to 5.5v table 35 switching characteristics (1), table 36 switching characteristics (2) are added. fig.80 circuit for measuring output switching characteristics (1), fig.81 circuit for measuring output switching characteristics (2) are added. fig.82 timing diagram (in single-chip mode) is revised. package outline 64f0g is added.
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